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公开(公告)号：US20160005484A1
公开(公告)日：2016-01-07
申请号：US14856261
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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2.发明授权Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same 有权非易失性存储器件包括外围电路，以接收与信号的上升沿和下降沿中的一个同步的地址，而不管是选择第一还是第二对准类型，并且包括其的非易失性存储器系统公开(公告)号：US09368168B2
公开(公告)日：2016-06-14
申请号：US14856218
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。
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公开(公告)号：US09715936B2
公开(公告)日：2017-07-25
申请号：US15062546
申请日：2016-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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公开(公告)号：US09281072B2
公开(公告)日：2016-03-08
申请号：US14856261
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。
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