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    MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE
    1.
    发明申请
    MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD OF THE MEMORY DEVICE 有权

    公开(公告)号：US20230026320A1

    公开(公告)日：2023-01-26

    申请号：US17869061

    申请日：2022-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungryun KIM

    IPC: G11C7/10 ,  G11C7/22

    Abstract: A memory device includes: a memory bank including a plurality of memory cells; and a memory interface circuit configured to store data in the plurality of memory cells based on a command/address signal and a data signal, wherein the memory interface circuit includes: first, second, third and fourth pads configured to receive first, second, third and fourth clock signals, respectively; a first buffer circuit configured to sample the command/address signal in response to an activation time of the first and third clock signals which have opposite phases from each other; and a second buffer circuit configured to sample the data signal in response to the activation time of the first clock signal, an activation time of the second clock signal, the activation time of the third clock signal and an activation time of the fourth clock signal.

    MEMORY DEVICE AND AN OPERATING METHOD THEREOF
    2.
    发明申请
    MEMORY DEVICE AND AN OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220068318A1

    公开(公告)日：2022-03-03

    申请号：US17215914

    申请日：2021-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun KIM ,  Kyungryun KIM ,  Junghwan PARK ,  Yeonkyu CHOI

    IPC: G11C5/14 ,  G11C7/06 ,  G11C7/22

    Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

    STORAGE AND PROGRAMMING METHOD THEREOF
    3.
    发明申请
    STORAGE AND PROGRAMMING METHOD THEREOF 审中-公开

    公开(公告)号：US20160284397A1

    公开(公告)日：2016-09-29

    申请号：US15176964

    申请日：2016-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun KIM ,  Sangyong YOON

    IPC: G11C11/56 ,  G11C16/16 ,  G11C16/30 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30

    Abstract: A program method of a storage device which includes at least one nonvolatile memory device and a memory controller to control the at least one nonvolatile memory device, the program method comprising: performing a first normal program operation to store first user data in a memory block; detecting, at the memory controller, a first event; performing a dummy program operation to store dummy data in at least one page of the memory block in response to the detection of the first event; and performing a second normal program operation to store second user data in the memory block after the dummy program operation, dummy program operations being operations in which random data is programmed into the memory block, normal program operations being operations in which data other than random data is programmed in the memory block.

    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230032415A1

    公开(公告)日：2023-02-02

    申请号：US17722805

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jaewoo JEONG ,  Kyungryun KIM ,  Yoochang SUNG ,  Changsik YOO

    IPC: G11C7/10

    Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

    MEMORY DEVICE HAVING GLOBAL LINE GROUPS IN WHICH DATA INPUT AND OUTPUT UNITS ARE DIFFERENT FROM EACH OTHER
    6.
    发明申请
    MEMORY DEVICE HAVING GLOBAL LINE GROUPS IN WHICH DATA INPUT AND OUTPUT UNITS ARE DIFFERENT FROM EACH OTHER 审中-公开

    公开(公告)号：US20190146703A1

    公开(公告)日：2019-05-16

    申请号：US16002298

    申请日：2018-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungryun KIM

    IPC: G06F3/06 ,  G11C7/12 ,  G06F11/10 ,  G06F12/02

    Abstract: A memory device includes first, second, third, and fourth memory cell groups and first and second transmitters. The first and second memory cell groups share first local lines. The third and fourth memory cell groups share second local lines. The first transmitter transmits first data to first global lines based on a read command. The first data is output from one of the first memory cell group and the second memory cell group on the first local lines. The second transmitter transmits second data to second global lines based on the read command. The second data is output from one of the third memory cell group and the fourth memory cell group on the second local lines. The number of the first global lines is different from the number of the second global lines.

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