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    MULTI-BIT FLIP-FLOPS
    1.
    发明申请
    MULTI-BIT FLIP-FLOPS 审中-公开

    公开(公告)号：US20170292993A1

    公开(公告)日：2017-10-12

    申请号：US15479310

    申请日：2017-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DOO-SEOK YOON ,  MIN-SU KIM ,  CHUNG-HEE KIM ,  DAE-SEONG LEE ,  HYUN LEE ,  MATTHEW BERZINS ,  JAMES LIM

    IPC: G01R31/3177 ,  G01R31/317 ,  H03K3/037

    CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/318541 ,  H03K3/0372

    Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

    MULTI-BIT FLIP-FLOPS AND SCAN CHAIN CIRCUITS
    2.
    发明申请
    MULTI-BIT FLIP-FLOPS AND SCAN CHAIN CIRCUITS 审中-公开
    多位片浮标和扫描链电路

    公开(公告)号：US20170016955A1

    公开(公告)日：2017-01-19

    申请号：US15281998

    申请日：2016-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MIN-SU KIM ,  MATTHEW BERZINS ,  JONG-WOO KIM

    IPC: G01R31/3177 ,  H03K19/21 ,  G01R31/317 ,  H03K3/037

    CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/21

    Abstract: A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.

    Abstract translation: 多位触发器包括共享时钟信号的多个多位触发器块。 多位触发器块中的每一个包括单个反相器和多个触发器。 单个反相器通过反相时钟信号产生反相时钟信号。 每个触发器包括主锁存部分和从锁存器部分，并且基于时钟信号和反相时钟信号操作主锁存器部分和从锁存器部分。 这里，触发器在时钟信号的上升沿被触发。 因此，作为主从触发器操作的多位触发器可以最小化（或降低）发送时钟信号的时钟通路中发生的功耗。

    FLIP-FLOP AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    5.
    发明申请
    FLIP-FLOP AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20180123569A1

    公开(公告)日：2018-05-03

    申请号：US15623412

    申请日：2017-06-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUN-CHUL HWANG ,  AH-REUM KIM ,  MIN-SU KIM

    IPC: H03K3/012 ,  H03K19/21 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/35625 ,  H03K19/21

    Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

    INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS INCLUDING INTEGRATED CIRCUIT
    6.
    发明申请
    INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS INCLUDING INTEGRATED CIRCUIT 审中-公开
    集成电路和电子设备，包括集成电路

    公开(公告)号：US20170003343A1

    公开(公告)日：2017-01-05

    申请号：US15140720

    申请日：2016-04-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUN-CHUL HWANG ,  DAE-SEONG LEE ,  MIN-SU KIM

    IPC: G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/318572 ,  G01R31/318541

    Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.

    Abstract translation: 集成电路和包括该集成电路的电子设备。 电子设备包括扫描输入处理电路，选择电路和扫描电路。 扫描输入处理单元被配置为响应于扫描使能信号输出扫描输入和第一逻辑值中的一个。 选择单元被配置为响应于扫描使能信号选择扫描输入处理单元的输出或数据输入中的一个。 扫描元件包括被配置为存储选择单元的输出的触发器。

    UNBALANCED MULTIPLEXER AND SCAN FLIP-FLOPS APPLYING THE SAME
    8.
    发明申请
    UNBALANCED MULTIPLEXER AND SCAN FLIP-FLOPS APPLYING THE SAME 审中-公开

    公开(公告)号：US20170276729A1

    公开(公告)日：2017-09-28

    申请号：US15332305

    申请日：2016-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MIN-SU KIM

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31725 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/31858

    Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

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