公开(公告)号：US20220310496A1

公开(公告)日：2022-09-29

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20210104489A1

公开(公告)日：2021-04-08

申请号：US16869988

申请日：2020-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo PARK ,  Jungho PARK ,  Dahye KIM ,  Minjun BAE

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US20220157772A1

公开(公告)日：2022-05-19

申请号：US17592947

申请日：2022-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo PARK ,  Jungho PARK ,  Dahye KIM ,  Minjun BAE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US20240203850A1

公开(公告)日：2024-06-20

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20220415835A1

公开(公告)日：2022-12-29

申请号：US17742852

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun BAE ,  Seokhyun LEE ,  Eungkyu KIM

IPC: H01L23/00

Abstract: Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

公开(公告)号：US20220293501A1

公开(公告)日：2022-09-15

申请号：US17453243

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  Kyoung Lim SUK ,  Minjun BAE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

公开(公告)号：US20200091066A1

公开(公告)日：2020-03-19

申请号：US16351709

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun LEE ,  Minjun BAE

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.