公开(公告)号：US20140273382A1

公开(公告)日：2014-09-18

申请号：US14289076

申请日：2014-05-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinho DO ,  Hajin LIM ,  WeonHong KIM ,  Kyungil HONG ,  Moonkyun SONG

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

摘要翻译： 准备包括NMOS晶体管区域和PMOS晶体管区域的衬底。 在PMOS晶体管区域上形成硅 - 锗层。 氮原子注入硅 - 锗层的上部。 在NMOS晶体管区域和PMOS晶体管区域上形成第一栅极电介质层。 在形成第一栅极介电层之前，将氮原子注入硅 - 锗层的上部。

公开(公告)号：US20140175569A1

公开(公告)日：2014-06-26

申请号：US14190346

申请日：2014-02-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WeonHong KIM ,  Dae-Kwon JOO ,  Hajin LIM ,  Jinho DO ,  Kyungil HONG ,  Moonkyun SONG

IPC分类号： H01L29/51

CPC分类号： H01L29/512 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

摘要翻译： 制造半导体器件的方法包括在半导体层上形成下界面层，下界面层为氮化物层，在下界面层上形成中间界面层，中间界面层为氧化物层，形成 中间界面层上的高k电介质层。 高k电介质层的介电常数高于下界面层和中间界面层的介电常数。

公开(公告)号：US20170062572A1

公开(公告)日：2017-03-02

申请号：US15132800

申请日：2016-04-19

申请人： Samsung Electronics Co., Ltd.

发明人： Dong Su Yoo ,  WeonHong KIM ,  Moonkyun SONG ,  Minjoo LEE ,  Soojung CHOI

IPC分类号： H01L29/40 ,  H01L21/441 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/401 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/441 ,  H01L21/762 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.

摘要翻译： 形成半导体器件的方法包括在有源图案上形成牺牲栅极图案，在牺牲栅极图案的相对侧壁上形成间隔物，在有源图案和间隔物上形成层间绝缘层，去除牺牲栅极图案以形成 栅极沟槽，其暴露有源图案的区域，在由栅极沟槽暴露的有源图案的区域上形成栅极电介质层，在小于1atm的压力下进行第一热处理以去除层间绝缘层中的杂质 在大于第一热处理的温度的温度下对栅介质层进行第二热处理，以及在栅沟中形成栅电极。