公开(公告)号：US20200083296A1

公开(公告)日：2020-03-12

申请号：US16685394

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung PARK ,  Seok-Won LEE ,  Seongjun SEO

IPC: H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US20150318226A1

公开(公告)日：2015-11-05

申请号：US14573134

申请日：2014-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Na BAEK ,  Seok-Won LEE ,  Eun-Seok CHO ,  Dong-Han KIM ,  Kyoung-Sei CHOI ,  Sa-Yoon KANG

IPC: H01L23/14 ,  H01L25/10 ,  H01L23/522

CPC classification number: H01L23/5389 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Abstract translation: 提供半导体封装，包括半导体芯片; 半导体芯片上的上部结构，上部结构具有第一热膨胀系数; 以及在所述半导体芯片下方的下部结构，所述下部结构具有小于或等于所述第一热膨胀系数的第二热膨胀系数。