公开(公告)号：US20240121952A1

公开(公告)日：2024-04-11

申请号：US18232568

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohyeon LEE ,  Seahoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.

公开(公告)号：US20240130133A1

公开(公告)日：2024-04-18

申请号：US18446911

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Seongpil CHANG ,  Sea Hoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.

公开(公告)号：US20180294274A1

公开(公告)日：2018-10-11

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Sunil SHIM ,  Jaeduk LEE ,  Jaehoon JANG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.