公开(公告)号：US20240155849A1

公开(公告)日：2024-05-09

申请号：US18372785

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Sunil SHIM ,  Jimin LEE ,  Yunsun JANG

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices on a first substrate, a lower interconnection structure connected to the circuit devices, and a lower bonding structure connected to the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, a stopper layer in contact with a lower surface of the second substrate, gate electrodes stacked and spaced apart from each other in a vertical direction, channel structures penetrating through the gate electrodes, and each including a channel layer, an upper interconnection structure below the gate electrodes, a peripheral contact plug spaced apart from the second substrate, and an upper bonding structure bonded to the lower bonding structure, wherein the channel structures penetrate at least a portion of the stopper layer, and wherein the peripheral contact plug penetrates at least a portion of the stopper layer.

公开(公告)号：US20220085064A1

公开(公告)日：2022-03-17

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk MOON ,  Juyoung LIM ,  Jongsoo KIM ,  Sunil SHIM ,  Haemin LEE ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20240341100A1

公开(公告)日：2024-10-10

申请号：US18386429

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin LEE ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG ,  Wonseok CHO ,  Moorym CHOI ,  Chulmin CHOI

IPC: H10B43/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes gate electrode structures, a first division pattern, a second division pattern, and a memory channel structure. Each gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures are spaced apart from each other in a third direction substantially parallel to the upper surface and crossing the second direction. The first division pattern extends in the second direction between the gate electrode structures on the substrate. The second division pattern extends in the third direction on the substrate, and is on sidewalls of end portions in the second direction of the gate electrode structures. The memory channel structure extends in the first direction through each gate electrode structure.

公开(公告)号：US20240057333A1

公开(公告)日：2024-02-15

申请号：US18134344

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes: a stack including interlayer insulating layers and conductive patterns, which are alternately stacked; a source conductive pattern on the stack; and vertical structures provided to penetrate the stack and connected to the source conductive pattern. Each of the vertical structures includes: a vertical channel pattern; a data storage pattern enclosing an outer side surface of the vertical channel pattern; a vertical insulating pillar in the vertical channel pattern; and a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern to connect the vertical channel pattern to the source conductive pattern.

公开(公告)号：US20240040791A1

公开(公告)日：2024-02-01

申请号：US18186531

申请日：2023-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG

IPC: H10B43/40 ,  H10B43/10 ,  H01L23/528 ,  H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/35 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/40 ,  H10B43/10 ,  H01L23/5283 ,  H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/35 ,  H10B41/27 ,  H10B41/40

Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure and including a cell array region and a cell array contact region. The cell array structure includes a stack structure including alternately stacked interlayer insulating layers and gate electrodes, a first source conductive pattern, a second source conductive pattern, and a third source conductive pattern sequentially stacked on the stack structure. The first to third source conductive patterns include different materials from each other. Vertical channel structures extending into a lower portion of the first source conductive pattern through the stack structure is included. The first to third source conductive patterns extend from the cell array region to the cell array contact region. The vertical channel structures include vertical semiconductor patterns that contact to the first source conductive pattern.

公开(公告)号：US20240349520A1

公开(公告)日：2024-10-17

申请号：US18370949

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Sunil SHIM ,  Seungwoo PAEK ,  Jimin LEE

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L24/48 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/059

Abstract: A semiconductor device includes bonded circuit and cell regions. The cell region includes a substrate, a base memory portion, and a bonding memory portion. Here, base memory portion includes a first gate stacking structure on the substrate and having first and second surfaces, a first channel structure penetrating the first gate stacking structure, and a base bonding pad on the second surface and connected to the first channel structure. The bonding memory portion includes a second gate stacking structure having a third surface bonded to the base memory portion and a fourth surface bonded to the circuit region, a second channel structure penetrating the second gate stacking structure, a first bonding pad connected to the second channel structure in the third surface and bonded to the base bonding pad, and a second bonding pad connected to the second channel structure in the fourth surface and bonded to the circuit region.

公开(公告)号：US20230282600A1

公开(公告)日：2023-09-07

申请号：US18196505

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Sunil SHIM

IPC: H01L23/00 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/562 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device including: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate on the bending prevention layer; gate electrodes spaced apart from each other in a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; and a channel extending through the gate electrodes in the second direction.

公开(公告)号：US20220310515A1

公开(公告)日：2022-09-29

申请号：US17701097

申请日：2022-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeshin LEE ,  Sunil SHIM ,  Juyoung LIM

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a structure including a stack structure including a first stack structure and a second stack structure on the first stack structure; a memory vertical structure penetrating the structure; a support vertical structure including a portion penetrating the structure and including an air gap; and a peripheral contact plug, wherein the first and second stack structures includes interlayer insulating layers and gate layers alternately stacked, a side of the memory vertical structure includes a slope changing portion, the peripheral contact plug includes an upper region disposed on a level higher than an upper surface of an uppermost gate layer, the upper region of the peripheral contact plug includes a first region, a second region and a connection region between the first and second regions, and the connection region has a slope different from a slope of at least one of the first and second regions.

公开(公告)号：US20210399008A1

公开(公告)日：2021-12-23

申请号：US17154159

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Young LIM ,  Jongsoo KIM ,  Jesuk MOON ,  Dongwoo KIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

公开(公告)号：US20220246537A1

公开(公告)日：2022-08-04

申请号：US17529941

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo KIM ,  Juyoung LIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L23/544 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.