公开(公告)号：US20220012128A1

公开(公告)日：2022-01-13

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20200319962A1

公开(公告)日：2020-10-08

申请号：US16695395

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02 ,  G11C13/00

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20230052799A1

公开(公告)日：2023-02-16

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20190004869A1

公开(公告)日：2019-01-03

申请号：US15855840

申请日：2017-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSIK KIM ,  JINWOO KIM ,  HEE HYUN NAM ,  KYUNGBO YANG ,  JI-SEUNG YOUN ,  YOUNGGEUN LEE

IPC: G06F9/50 ,  G06F3/06 ,  G06F1/30

Abstract: A storage device includes a nonvolatile memory and a controller. The controller includes a job manager circuit and a processor. The job manager circuit manages a first-type job associated with the nonvolatile memory, and the processor processes a second-type job associated with the nonvolatile memory. The job manager circuit manages the first-type job without intervention of the processor. The processor provides a management command to the job manager circuit in response to a notification received from the job manager circuit, such that the second-type job is processed.

公开(公告)号：US20210406125A1

公开(公告)日：2021-12-30

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20190004736A1

公开(公告)日：2019-01-03

申请号：US15860498

申请日：2018-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGGEUN LEE ,  JINWOO KIM ,  YOUNGSIK KIM ,  HWAN-CHUNG KIM ,  JEONGHOON CHO

IPC: G06F3/06

Abstract: A storage device includes nonvolatile memories and a controller. The controller previously manages a correspondence relationship between physical addresses indicating the memory regions and stream identifiers, before first write data is received by the controller. The controller controls the nonvolatile memories such that the first write data is stored in a first memory region of a physical address which is managed corresponding to a first stream identifier of the first write data in the correspondence relationship. The first write data is transferred to the nonvolatile memories based on the correspondence relationship, regardless of whether second write data having a second stream identifier is received by the controller.

公开(公告)号：US20220027232A1

公开(公告)日：2022-01-27

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20200341843A1

公开(公告)日：2020-10-29

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20160358657A1

公开(公告)日：2016-12-08

申请号：US15083834

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  SEONG YEON KIM ,  JAEGEUN PARK ,  HYO-DEOK SHIN ,  YOUNGGEUN LEE ,  YOUNGJIN CHO

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1063

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Abstract translation: 非易失性存储器系统包括第一和第二非易失性存储器件以及被配置为通过一个通道来控制第一和第二非易失性存储器件的存储器控​​制器。 在程序操作期间，存储器控制器通过通道向第一非易失性存储器件发送用于将第一非易失性存储器件中的第一页数据向上设置的第一信号。 当第一非易失性存储装置响应于第一信号设置第一页数据时，存储器控制器将用于将第二页数据向上设置在第二非易失存储装置中的第二信号发送到第二非易失存储装置。