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    Write-once read-many amorphous chalcogenide-based memory
    2.
    发明授权
    Write-once read-many amorphous chalcogenide-based memory 有权

    公开(公告)号：US10290348B1

    公开(公告)日：2019-05-14

    申请号：US15972596

    申请日：2018-05-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Federico Nardi

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: Systems and methods for providing a one-time programmable chalcogenide-based memory with improved memory cell IV characteristics are described. The memory cells of the one-time programmable chalcogenide-based memory may include a chalcogenide-based material. The chalcogenide-based material may comprise a germanium-antimony-tellurium compound (GST), a chalcogenide glass, or a chalcogenide alloy such as Ge10Se54As36 or Ge17Te50As33. The chalcogenide-based memory may be written as a one-time programmable memory in which forming operations are performed on only memory cells that are to be programmed to store a first binary value (e.g., binary “1” data values) and not performed on other memory cells that are to store a second binary value different from the first binary value (e.g., binary “0” data values).

    Phase change memory electrode with multiple thermal interfaces
    4.
    发明授权
    Phase change memory electrode with multiple thermal interfaces 有权

    公开(公告)号：US10147876B1

    公开(公告)日：2018-12-04

    申请号：US15693376

    申请日：2017-08-31

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Lidu Huang ,  Mac D. Apodaca ,  Toshiki Hirano ,  Ailian Zhao ,  Guy Charles Wicker ,  Federico Nardi

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.

    Threshold switch for memory
    6.
    发明授权
    Threshold switch for memory 有权

    公开(公告)号：US10943952B2

    公开(公告)日：2021-03-09

    申请号：US16435843

    申请日：2019-06-10

    Applicant: SanDisk Technologies LLC

    Inventor： Federico Nardi ,  Ming-Che Wu ,  Tim Minvielle ,  Zhaoqiang Bai

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.

    IN-STORAGE LOGIC FOR HARDWARE ACCELERATORS
    8.
    发明申请
    IN-STORAGE LOGIC FOR HARDWARE ACCELERATORS 有权

    公开(公告)号：US20210233592A1

    公开(公告)日：2021-07-29

    申请号：US16775639

    申请日：2020-01-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Federico Nardi ,  Won Ho Choi

    IPC: G11C16/26 ,  G11C16/04

    Abstract: Systems and methods for performing in-storage logic operations using one or more memory cell transistors and a programmable sense amplifier are described. The logic operations may comprise basic Boolean logic operations (e.g., OR and AND operations) or secondary Boolean logic operations (e.g., XOR and IMP operations). The one or more memory cell transistors may be used for storing user data during a first time period and then used for performing a logic operation during a second time period subsequent to the first time period. During the logic operation, a first memory cell transistor of the one or more memory cell transistors may be programmed with a threshold voltage that corresponds with a first input operand value and then a gate voltage bias may be applied to the first memory cell transistor during the logic operation that corresponds with a second input operand value.

    Resistive memory device including a lateral air gap around a memory element and method of making thereof
    10.
    发明授权
    Resistive memory device including a lateral air gap around a memory element and method of making thereof 有权

    公开(公告)号：US10050194B1

    公开(公告)日：2018-08-14

    申请号：US15478637

    申请日：2017-04-04

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Federico Nardi ,  Chu-Chen Fu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: First electrically conductive lines can be formed over a substrate. A two-dimensional array of vertical stacks can be formed, each of which includes a first electrode, an in-process resistive memory material portion, and a second electrode over the first electrically conductive line. The sidewalls of the in-process resistive memory material portions are laterally recessed with respect to sidewalls of the first electrode and the second electrode to form resistive memory material portions having reduced lateral dimensions. A dielectric material layer is formed by an anisotropic deposition to form annular cavities that laterally surround a respective one of the resistive memory material portions. Second electrically conductive lines can be formed on the second electrodes.

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