公开(公告)号：US20220148665A1

公开(公告)日：2022-05-12

申请号：US17091834

申请日：2020-11-06

Applicant: SanDisk Technologies LLC

Inventor： Rajdeep Gautam ,  Akira Okada

IPC: G11C16/34 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30

Abstract: A method for programming a target memory cell in a memory array of a non-volatile memory system, the method comprising defining a default read biasing voltage value and a default verify biasing voltage value for each program state of a target memory cell of a memory structure, determining a location of a target memory cell within the memory structure and, based upon the determined location of the target memory cell, applying a first incremental offset voltage to the default read biasing voltage value with respect to each program state, and applying a second incremental offset voltage to the default verify biasing voltage value with respect to each program state.

公开(公告)号：US10373697B1

公开(公告)日：2019-08-06

申请号：US15897550

申请日：2018-02-15

Applicant: SanDisk Technologies LLC

Inventor： Chun-Hung Lai ,  Rajdeep Gautam ,  Ching-Huang Lu ,  Shih-Chung Lee

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  G11C11/56 ,  G11C7/14

CPC classification number: G11C16/3445 ,  G11C7/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

公开(公告)号：US20230041950A1

公开(公告)日：2023-02-09

申请号：US17397846

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/522 ,  G11C8/14 ,  G11C5/06

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20230038557A1

公开(公告)日：2023-02-09

申请号：US17397777

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H01L27/11582 ,  G11C16/08 ,  G11C16/24 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US11551768B2

公开(公告)日：2023-01-10

申请号：US17091834

申请日：2020-11-06

Applicant: SanDisk Technologies LLC

Inventor： Rajdeep Gautam ,  Akira Okada

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/26 ,  G11C16/20

Abstract: A method for programming a target memory cell in a memory array of a non-volatile memory system, the method comprising defining a default read biasing voltage value and a default verify biasing voltage value for each program state of a target memory cell of a memory structure, determining a location of a target memory cell within the memory structure and, based upon the determined location of the target memory cell, applying a first incremental offset voltage to the default read biasing voltage value with respect to each program state, and applying a second incremental offset voltage to the default verify biasing voltage value with respect to each program state.

公开(公告)号：US20220059157A1

公开(公告)日：2022-02-24

申请号：US16996412

申请日：2020-08-18

Applicant: SanDisk Technologies LLC

Inventor： Zhixin Cui ,  Rajdeep Gautam ,  Hardwell Chibvongodze

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/02

Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation,

公开(公告)号：US10978152B1

公开(公告)日：2021-04-13

申请号：US16682730

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US11361816B2

公开(公告)日：2022-06-14

申请号：US16996412

申请日：2020-08-18

Applicant: SanDisk Technologies LLC

Inventor： Zhixin Cui ,  Rajdeep Gautam ,  Hardwell Chibvongodze

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C5/02 ,  G11C11/408 ,  G11C11/4074

Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.

公开(公告)号：US11049580B1

公开(公告)日：2021-06-29

申请号：US16914408

申请日：2020-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.

公开(公告)号：US11004525B1

公开(公告)日：2021-05-11

申请号：US16796897

申请日：2020-02-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.