公开(公告)号：US20200295012A1

公开(公告)日：2020-09-17

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/768

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200091157A1

公开(公告)日：2020-03-19

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200286901A1

公开(公告)日：2020-09-10

申请号：US16291673

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shigeki SHIMOMURA ,  Satoru MAYUZUMI ,  Hiroyuki OGAWA

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  G11C11/16

Abstract: A vertically alternating sequence of multi-fingered silicon-germanium layers and multi-fingered silicon layers is formed over a substrate. The multi-fingered silicon-germanium layers include silicon-germanium wires, and the multi-fingered silicon layers include silicon wires. Tubular memory films and multi-fingered gate electrodes are formed. Each gate electrode includes a respective gate electrode bar which overlies the silicon wires and a respective set of vertically-extending gate electrode fingers which is adjoined to a bottom portion of the respective gate electrode bar and spaced apart by the silicon wires. The multi-fingered silicon-germanium layers are removed selective to multi-fingered silicon layers. First active regions are formed at an end portion of each of the silicon wires. Second active regions are formed on silicon plate portions of the multi-fingered silicon layers.