公开(公告)号：US10319420B2

公开(公告)日：2019-06-11

申请号：US15789638

申请日：2017-10-20

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Chun-Ju Chu

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C7/08 ,  G11C7/02 ,  G11C7/12 ,  G11C29/02

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line. Doing so may allow the memory cell characterization circuitry to cancel out background noise current generated on the bit line during the sense operation.

公开(公告)号：US10241938B1

公开(公告)日：2019-03-26

申请号：US15849413

申请日：2017-12-20

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Yingchang Chen

IPC: G06F13/42 ,  G06F13/16 ,  G06F12/02

Abstract: Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer stage width may be a width of an internal bus for a non-volatile memory element. A buffer may include two or more read pointers, updated by an internal controller at different times in response to different portions of a clock signal. A parallel-in serial-out (PISO) component may receive data via an internal data path having a data path width equal to an internal bus width, and may output the data in a series of transfers controlled according to a clock signal, via an output bus having an output bus width narrower than an internal bus width. A PISO component may receive data from a portion of a buffer stage in response to an internal controller updating a read pointer to point to the buffer stage.

公开(公告)号：US10734048B2

公开(公告)日：2020-08-04

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/08 ,  G11C7/12

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US10269444B2

公开(公告)日：2019-04-23

申请号：US15491691

申请日：2017-04-19

Applicant: SanDisk Technologies LLC

Inventor： Anurag Nigam ,  Yukeun Sim ,  Jingwen Ouyang ,  Yingchang Chen

IPC: G11C29/38 ,  G11C7/10 ,  G11C13/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

Abstract: Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

公开(公告)号：US10032489B1

公开(公告)日：2018-07-24

申请号：US15459857

申请日：2017-03-15

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Xiaoxia Wu

IPC: G11C5/14 ,  G11C7/02 ,  G11C7/06 ,  G11C7/12

Abstract: This disclosure provides a method and apparatus for detecting a transition of a memory cell current from a first state to a second state. An example apparatus includes a memory cell, a supplemental current source, a comparator, a reference voltage and a reference current source in a configuration that allows for real time detection of the transition of a memory cell. Detection of a memory cell current transition is captured when the output of the comparator transitions from one state to a second state in response to a sensing voltage exceeding the reference voltage.

公开(公告)号：US20210193230A1

公开(公告)日：2021-06-24

申请号：US16724896

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Seungpil Lee ,  Ali Al-Shamma

IPC: G11C16/26 ,  G11C16/04

Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

公开(公告)号：US20190371380A1

公开(公告)日：2019-12-05

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/12 ,  G11C7/08

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US20190130946A1

公开(公告)日：2019-05-02

申请号：US15799688

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Anurag Nigam ,  Yingchang Chen

IPC: G11C7/08 ,  G11C7/10 ,  G11C7/22

Abstract: A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.

公开(公告)号：US10254967B2

公开(公告)日：2019-04-09

申请号：US15402180

申请日：2017-01-09

Applicant: SanDisk Technologies LLC

Inventor： Jingwen Ouyang ,  Tz-Yi Liu ,  Henry Zhang ,  Yingchang Chen

IPC: G11C16/34 ,  G11C16/10 ,  G06F3/06

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

公开(公告)号：US10803912B2

公开(公告)日：2020-10-13

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.