公开(公告)号：US10269444B2

公开(公告)日：2019-04-23

申请号：US15491691

申请日：2017-04-19

Applicant: SanDisk Technologies LLC

Inventor： Anurag Nigam ,  Yukeun Sim ,  Jingwen Ouyang ,  Yingchang Chen

IPC: G11C29/38 ,  G11C7/10 ,  G11C13/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

Abstract: Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

公开(公告)号：US20180174668A1

公开(公告)日：2018-06-21

申请号：US15491691

申请日：2017-04-19

Applicant: SanDisk Technologies LLC

Inventor： Anurag Nigam ,  Yukeun Sim ,  Jingwen Ouyang ,  Yingchang Chen

IPC: G11C29/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C29/38 ,  G11C7/1009 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/025 ,  G11C29/026 ,  G11C29/44 ,  G11C29/76 ,  G11C29/789 ,  G11C29/804 ,  G11C29/81 ,  G11C29/82 ,  G11C2029/1204 ,  G11C2029/1208 ,  G11C2029/4402 ,  G11C2213/71

Abstract: Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

公开(公告)号：US10290332B1

公开(公告)日：2019-05-14

申请号：US15799688

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Anurag Nigam ,  Yingchang Chen

IPC: G11C5/06 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

Abstract: A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.

公开(公告)号：US10241938B1

公开(公告)日：2019-03-26

申请号：US15849413

申请日：2017-12-20

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Yingchang Chen

IPC: G06F13/42 ,  G06F13/16 ,  G06F12/02

Abstract: Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer stage width may be a width of an internal bus for a non-volatile memory element. A buffer may include two or more read pointers, updated by an internal controller at different times in response to different portions of a clock signal. A parallel-in serial-out (PISO) component may receive data via an internal data path having a data path width equal to an internal bus width, and may output the data in a series of transfers controlled according to a clock signal, via an output bus having an output bus width narrower than an internal bus width. A PISO component may receive data from a portion of a buffer stage in response to an internal controller updating a read pointer to point to the buffer stage.

公开(公告)号：US20190130946A1

公开(公告)日：2019-05-02

申请号：US15799688

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Anurag Nigam ,  Yingchang Chen

IPC: G11C7/08 ,  G11C7/10 ,  G11C7/22

Abstract: A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.