公开(公告)号：US20170179151A1

公开(公告)日：2017-06-22

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09818693B2

公开(公告)日：2017-11-14

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09818759B2

公开(公告)日：2017-11-14

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170179026A1

公开(公告)日：2017-06-22

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US10038006B2

公开(公告)日：2018-07-31

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko Furihata ,  Jixin Yu ,  Hiroyuki Ogawa ,  James Kai ,  Jin Liu ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/02

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09978766B1

公开(公告)日：2018-05-22

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Takeshi Kawamura ,  Yoko Furihata ,  Kota Funayama

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.