公开(公告)号：US20240224491A1

公开(公告)日：2024-07-04

申请号：US18602522

申请日：2024-03-12

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H10B10/00 ,  H01L27/105

CPC classification number: H10B10/18 ,  H01L27/105

Abstract: A semiconductor device includes a peripheral circuit area, a bit cell area, and a separating area positioned between the peripheral circuit area and the bit cell. A first power switch circuit for the peripheral circuit area is connected to a first power supply line, and a second power supply line and a first ground line provided on the substrate; and connects the first power supply line and the second power supply line. The second power switch circuit for the bit cell area is connected to a third power supply line, a fourth power supply line, and a second ground line provided on the substrate; and connects the third power supply line and the fourth power supply line.

公开(公告)号：US20190081029A1

公开(公告)日：2019-03-14

申请号：US16189900

申请日：2018-11-13

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Tomoyasu KITAURA ,  Hirotaka TAKENO

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/00

Abstract: A circuit block including standard cells (1) arranged therein is provided with switch cells (20) capable of switching between electrical connection and disconnection between power supply lines (3) extending in an X-direction and power supply straps (11) extending in a Y-direction. Each of the power supply straps (11) is provided with a single switch cell (20) arranged every M sets of power supply lines (3) (M is an integer of 3 or more). In the Y-direction, the switch cells (20) are arranged at different positions in the power supply straps (11) adjacent to each other, and are arranged at the same position every M power supply straps (11) in the X-direction.

公开(公告)号：US20250088190A1

公开(公告)日：2025-03-13

申请号：US18957281

申请日：2024-11-22

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20240258236A1

公开(公告)日：2024-08-01

申请号：US18608113

申请日：2024-03-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate; a third power supply line provided on a second surface of the substrate, and connected to the first power supply line through a via; a fourth power supply line; a first area including the second power supply line, the first ground line, the third power supply line; a second area including the fourth power supply line and the second ground line; a third area positioned between the first area and the second area in plan view; and a power switch circuit including a switch transistor connected between the first power supply line and the second power supply line.

公开(公告)号：US20230120959A1

公开(公告)日：2023-04-20

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Junji IWAHORI

IPC: H03K17/16 ,  H03K17/687

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20220239297A1

公开(公告)日：2022-07-28

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20250056879A1

公开(公告)日：2025-02-13

申请号：US18929016

申请日：2024-10-28

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20230223381A1

公开(公告)日：2023-07-13

申请号：US18179013

申请日：2023-03-06

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/50 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20220231053A1

公开(公告)日：2022-07-21

申请号：US17577994

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Toshio HINO

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

公开(公告)号：US20190123741A1

公开(公告)日：2019-04-25

申请号：US16206874

申请日：2018-11-30

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Tomoyasu KITAURA ,  Hirotaka TAKENO

IPC: H03K17/687 ,  H01L27/02

Abstract: Power switch cells (20) respectively includes power switches (21), each of which is capable of performing switching between electrical connection and disconnection between a global power supply line (11) and a local power supply line (8) in accordance with a control signal (CTR). The power switches (21) are connected in a chain state to constitute a chain connection through which the control signal (CTR) is sequentially transmitted. A starting point switch (21a) in the chain connection has a greater distance to an edge (BE) of a region occupied by a power domain than an ending point switch (21b).