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    PROCESS AND TEMPERATURE COMPENSATED WORD LINE UNDERDRIVE SCHEME FOR SRAM
    1.
    发明公开
    PROCESS AND TEMPERATURE COMPENSATED WORD LINE UNDERDRIVE SCHEME FOR SRAM 审中-公开

    公开(公告)号：US20240071480A1

    公开(公告)日：2024-02-29

    申请号：US18231461

    申请日：2023-08-08

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish KUMAR ,  Dipti ARYA

    IPC: G11C11/418

    CPC classification number: G11C11/418

    Abstract: Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.

    RETENTION OF DATA DURING STAND-BY MODE
    4.
    发明申请
    RETENTION OF DATA DURING STAND-BY MODE 审中-公开
    在待机模式下保留数据

    公开(公告)号：US20140376322A1

    公开(公告)日：2014-12-25

    申请号：US14480881

    申请日：2014-09-09

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Ashish KUMAR

    IPC: G11C5/14

    CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/02 ,  G11C2207/2227

    Abstract: An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode.

    Abstract translation: 本公开的实施例涉及在备用模式中将数据保留在存储阵列中。 存储设备包括一个或多个存储阵列节点，以及可操作地耦合到存储阵列节点的轨至轨电压调节器。 轨到轨电压调节器被配置为在待机模式期间选择性地改变在每个所述存储阵列节点处提供的电压。 存储设备还可以包括可操作地耦合到所述轨到轨电压调节器的存储阵列和可操作地耦合到所述存储阵列节点并且被配置为控制所述轨至轨电压调节器的轨至轨电压监视器，以提供足够的电压以在 待机模式。

    NOISE TOLERANT SENSE CIRCUIT
    5.
    发明申请
    NOISE TOLERANT SENSE CIRCUIT 审中-公开
    噪声容忍感知电路

    公开(公告)号：US20140286116A1

    公开(公告)日：2014-09-25

    申请号：US14107982

    申请日：2013-12-16

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish KUMAR ,  Manish Umedlal PATEL

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C8/12 ,  G11C2207/005

    Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.

    Abstract translation: 已经公开了一种用于感测电路的装置和方法。 在实现中，感测电路包括读出放大器和至少一个解耦装置。 解耦器件通过至少一个参考线耦合到读出放大器。 读出放大器读取数据值，去耦器件在读取操作期间将读出放大器与电源解耦。

    HIGH SPEED SRAM USING ENHANCE WORDLINE/GLOBAL BUFFER DRIVE
    6.
    发明申请
    HIGH SPEED SRAM USING ENHANCE WORDLINE/GLOBAL BUFFER DRIVE 有权

    公开(公告)号：US20220020405A1

    公开(公告)日：2022-01-20

    申请号：US17375149

    申请日：2021-07-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish KUMAR ,  Dipti ARYA

    IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C5/14

    Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

    REDUCED RETENTION LEAKAGE SRAM
    7.
    发明申请
    REDUCED RETENTION LEAKAGE SRAM 审中-公开

    公开(公告)号：US20200327927A1

    公开(公告)日：2020-10-15

    申请号：US16809006

    申请日：2020-03-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish KUMAR ,  Mohammad Aftab ALAM

    IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/413 ,  G11C5/14

    Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

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