公开(公告)号：US11495508B2

公开(公告)日：2022-11-08

申请号：US17039289

申请日：2020-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Simone Rascuna′ ,  Claudio Chibbaro ,  Alfio Guarnera ,  Mario Giuseppe Saggio ,  Francesco Lizio

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US12125762B2

公开(公告)日：2024-10-22

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone Rascuna' ,  Claudio Chibbaro ,  Alfio Guarnera ,  Mario Giuseppe Saggio ,  Francesco Lizio

IPC: H01L21/04 ,  H01L21/56 ,  H01L23/31 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L23/3171 ,  H01L21/045 ,  H01L21/56 ,  H01L29/1608

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US11854809B2

公开(公告)日：2023-12-26

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11545362B2

公开(公告)日：2023-01-03

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11329131B2

公开(公告)日：2022-05-10

申请号：US17096635

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L29/08 ,  H01L29/16

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

公开(公告)号：US11018008B2

公开(公告)日：2021-05-25

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo Zanetti ,  Simone Rascuná ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11798981B2

公开(公告)日：2023-10-24

申请号：US17346771

申请日：2021-06-14

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Angelo Magri' ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0607 ,  H01L29/1608

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：US08828809B2

公开(公告)日：2014-09-09

申请号：US13887066

申请日：2013-05-03

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Alfio Guarnera

IPC: H01L21/332 ,  H01L21/761 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/761 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/7811

Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

Abstract translation: 一种半导体功率器件的实施例，其具备：由具有第一导电性的半导体材料制成的结构体，其具有容纳一个或多个基本电子部件的有源区域和在有源区域外部限定的边缘区域; 并且由掺杂有与第一导电性相反的第二导电性的区域构成的电荷平衡结构在有源区域和边缘区域中延伸穿过结构体，以产生实质的电荷平衡。 电荷平衡结构是在活性区域和边缘区域中彼此平行延伸的柱状壁，而没有任何相互交叉。

公开(公告)号：US12255233B2

公开(公告)日：2025-03-18

申请号：US17579474

申请日：2022-01-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Alessia Maria Frazzetto ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L21/00 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

公开(公告)号：US12249634B2

公开(公告)日：2025-03-11

申请号：US17669239

申请日：2022-02-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mario Giuseppe Saggio ,  Alfio Guarnera ,  Cateno Marco Camalleri

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/40 ,  H01L29/43 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.