公开(公告)号：US11798981B2

公开(公告)日：2023-10-24

申请号：US17346771

申请日：2021-06-14

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Angelo Magri' ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0607 ,  H01L29/1608

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：US12148824B2

公开(公告)日：2024-11-19

申请号：US17665398

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti

IPC: H01L29/78 ,  H01L21/70 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

公开(公告)号：US12255233B2

公开(公告)日：2025-03-18

申请号：US17579474

申请日：2022-01-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Alessia Maria Frazzetto ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L21/00 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

公开(公告)号：US08580640B2

公开(公告)日：2013-11-12

申请号：US13706312

申请日：2012-12-05

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti ,  Ferruccio Frisina

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

Abstract translation: 一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。 该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二掩模; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

公开(公告)号：US11854809B2

公开(公告)日：2023-12-26

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11545362B2

公开(公告)日：2023-01-03

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11329131B2

公开(公告)日：2022-05-10

申请号：US17096635

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti ,  Alfio Guarnera

IPC: H01L29/08 ,  H01L29/16

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

公开(公告)号：US11251296B2

公开(公告)日：2022-02-15

申请号：US16528410

申请日：2019-07-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

公开(公告)号：US11018008B2

公开(公告)日：2021-05-25

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo Zanetti ,  Simone Rascuná ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20200044077A1

公开(公告)日：2020-02-06

申请号：US16528410

申请日：2019-07-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.