公开(公告)号：US20230004354A1

公开(公告)日：2023-01-05

申请号：US17940654

申请日：2022-09-08

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER ,  Giuseppe DESOLI

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US20220139453A1

公开(公告)日：2022-05-05

申请号：US17578086

申请日：2022-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER

IPC: G11C13/00 ,  G06F9/50 ,  G06N3/063 ,  G11C29/00 ,  G11C29/26

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US20230186983A1

公开(公告)日：2023-06-15

申请号：US18167580

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY ,  Nitin CHAWLA

IPC: G11C11/419 ,  H10B10/00

CPC classification number: G11C11/419 ,  H10B10/12

Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

公开(公告)号：US20210065776A1

公开(公告)日：2021-03-04

申请号：US16994488

申请日：2020-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C5/02

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US20210225453A1

公开(公告)日：2021-07-22

申请号：US17222119

申请日：2021-04-05

Applicant: STMicroelectronics International N.V.

Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

IPC: G11C29/38 ,  G11C29/14

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

公开(公告)号：US20190198508A1

公开(公告)日：2019-06-27

申请号：US16211113

申请日：2018-12-05

Applicant: STMicroelectronics International N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C11/412

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20220328118A1

公开(公告)日：2022-10-13

申请号：US17846578

申请日：2022-06-22

Applicant: STMicroelectronics International N.V.

Inventor： Tanmoy ROY ,  Anuj GROVER

IPC: G11C29/36 ,  G11C29/10 ,  G11C29/44

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.

公开(公告)号：US20210233600A1

公开(公告)日：2021-07-29

申请号：US17157868

申请日：2021-01-25

Applicant: STMicroelectronics International N.V.

Inventor： Tanmoy ROY ,  Anuj GROVER

IPC: G11C29/36 ,  G11C29/10 ,  G11C29/44

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.

公开(公告)号：US20230091970A1

公开(公告)日：2023-03-23

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20220238150A1

公开(公告)日：2022-07-28

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.