公开(公告)号：US20140175541A1

公开(公告)日：2014-06-26

申请号：US14108598

申请日：2013-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo Matri' ,  Francesco Lizio

IPC: H01L23/00 ,  H01L29/78 ,  H01L21/82 ,  H01L21/28

CPC classification number: H01L23/562 ,  H01L21/28008 ,  H01L21/82 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.

Abstract translation: 在具有主表面的半导体材料的晶片（100; 200a; 200b）上集成一组电子器件的方法包括从主表面形成延伸到晶片中的多个沟槽。 在每个沟槽内形成至少一层电绝缘材料。 在叠加在至少一层绝缘材料上的每个沟槽内形成至少一层导电材料层。 多个沟槽的形成包括形成划分成子集的沟槽的沟槽。 第一子集的沟槽沿着与第二子集的沟槽的取向不同的第一公共方向定向。

公开(公告)号：US12125762B2

公开(公告)日：2024-10-22

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone Rascuna' ,  Claudio Chibbaro ,  Alfio Guarnera ,  Mario Giuseppe Saggio ,  Francesco Lizio

IPC: H01L21/04 ,  H01L21/56 ,  H01L23/31 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L23/3171 ,  H01L21/045 ,  H01L21/56 ,  H01L29/1608

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US11495508B2

公开(公告)日：2022-11-08

申请号：US17039289

申请日：2020-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Simone Rascuna′ ,  Claudio Chibbaro ,  Alfio Guarnera ,  Mario Giuseppe Saggio ,  Francesco Lizio

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US09070694B2

公开(公告)日：2015-06-30

申请号：US14108598

申请日：2013-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo Magri′ ,  Francesco Lizio

IPC: H01L21/82 ,  H01L23/00 ,  H01L29/423 ,  H01L27/02 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/562 ,  H01L21/28008 ,  H01L21/82 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.

Abstract translation: 在具有主表面的半导体材料的晶片（100; 200a; 200b）上集成一组电子器件的方法包括从主表面形成延伸到晶片中的多个沟槽。 在每个沟槽内形成至少一层电绝缘材料。 在叠加在至少一层绝缘材料上的每个沟槽内形成至少一层导电材料层。 多个沟槽的形成包括形成划分成子集的沟槽的沟槽。 第一子集的沟槽沿着与第二子集的沟槽的取向不同的第一公共方向定向。

公开(公告)号：US09018048B2

公开(公告)日：2015-04-28

申请号：US14032123

申请日：2013-09-19

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Lizio

IPC: H01L21/332 ,  H01L29/66 ,  H01L21/266 ,  H01L29/861 ,  H01L21/265 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/6609 ,  H01L29/7802 ,  H01L29/861

Abstract: A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.

Abstract translation: 一种制造半导体器件的方法，其中半导体层形成在半导体材料体上; 在半导体层上形成第一掩模; 使用第一掩模将第一导电区域植入体内; 至少在与主体表面平行的平面中的突起中，第二掩模横向并互补地形成于第一掩模; 使用第二掩模将第二导电区域注入到与第一导电区域相邻和互补的位置的本体中; 间隔物形成在第二掩模区域的侧面上，以形成与第二掩模对准的第三掩模; 并且使用第三掩模去除半导体层的部分以形成栅极区域。