公开(公告)号：US20190267311A1

公开(公告)日：2019-08-29

申请号：US16264822

申请日：2019-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US20210057355A1

公开(公告)日：2021-02-25

申请号：US16996712

申请日：2020-08-18

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey ARELLANO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

公开(公告)号：US20180331020A1

公开(公告)日：2018-11-15

申请号：US15594351

申请日：2017-05-12

Applicant: STMicroelectronics, Inc.

Inventor： Aaron CADAG ,  Ian Harvey ARELLANO ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92247

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US20240178006A1

公开(公告)日：2024-05-30

申请号：US18435915

申请日：2024-02-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/4821 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L21/561 ,  H01L21/565 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US20240162168A1

公开(公告)日：2024-05-16

申请号：US18531561

申请日：2023-12-06

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey ARELLANO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

公开(公告)号：US20220320014A1

公开(公告)日：2022-10-06

申请号：US17845867

申请日：2022-06-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey ARELLANO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

公开(公告)号：US20210313255A1

公开(公告)日：2021-10-07

申请号：US17353684

申请日：2021-06-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.