公开(公告)号：US11195872B2

公开(公告)日：2021-12-07

申请号：US16547231

申请日：2019-08-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Stephane Hulot ,  Andrej Suler ,  Nicolas Virollet

IPC: H01L27/146

Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

公开(公告)号：US11145780B2

公开(公告)日：2021-10-12

申请号：US16789045

申请日：2020-02-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US10361238B2

公开(公告)日：2019-07-23

申请号：US15703246

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US10193009B1

公开(公告)日：2019-01-29

申请号：US15945972

申请日：2018-04-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US10162048B2

公开(公告)日：2018-12-25

申请号：US15392032

申请日：2016-12-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Boris Rodrigues ,  Marie Guillon ,  Yvon Cazaux ,  Benoit Giffard

IPC: G01S7/48 ,  H01L27/146 ,  H04N5/374 ,  G01S7/491 ,  G01S7/486

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

公开(公告)号：US20180323228A1

公开(公告)日：2018-11-08

申请号：US16031710

申请日：2018-07-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14812

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US10043837B2

公开(公告)日：2018-08-07

申请号：US15488691

申请日：2017-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/148 ,  H01L27/146

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US20180090435A1

公开(公告)日：2018-03-29

申请号：US15275619

申请日：2016-09-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L25/0657

Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.

公开(公告)号：US09917125B2

公开(公告)日：2018-03-13

申请号：US14959687

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1464 ,  H01L27/14685

Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.

公开(公告)号：US20180061875A1

公开(公告)日：2018-03-01

申请号：US15251745

申请日：2016-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146 ,  H04N5/225

CPC classification number: H01L27/14614 ,  H01L27/14689

Abstract: A transfer gate transistor includes a semiconductor substrate including a charge collection source region, a portion forming a channel region and a top region forming a drain region. A trench in the substrate surrounds the top region and the portion of the substrate. A vertical insulated gate structure for the transistor is formed in the trench. The vertical insulated gate structure includes an insulating liner on sidewalls and a bottom of said trench and an electrode including an upper conductive part and a lower conductive part. A width of the upper conductive part parallel to an upper surface of the substrate increases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the upper conductive part decreases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the lower conductive part is substantially constant.