公开(公告)号：US20230068198A1

公开(公告)日：2023-03-02

申请号：US17890113

申请日：2022-08-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Simon Guillaumet ,  Benjamin Vianne ,  Stephane Zoll

IPC: G02B5/02

Abstract: The present description concerns an optical diffuser including a first layer having an electrically-conductive track formed therein, and a second layer, having the first layer resting thereon resting thereon, and having at least two electrically-conductive pillars extending across the entire thickness of the second layer formed therein. The second layer includes at least one first region located under the conductive track comprising no pillar.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20180286878A1

公开(公告)日：2018-10-04

申请号：US15995452

申请日：2018-06-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/11539 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/788

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US10014308B2

公开(公告)日：2018-07-03

申请号：US15228236

申请日：2016-08-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/105 ,  H01L27/11539 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L27/11539 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20170200730A1

公开(公告)日：2017-07-13

申请号：US15228236

申请日：2016-08-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11539 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.