公开(公告)号：US20230068198A1

公开(公告)日：2023-03-02

申请号：US17890113

申请日：2022-08-17

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Simon Guillaumet ,  Benjamin Vianne ,  Stephane Zoll

IPC分类号： G02B5/02

摘要： The present description concerns an optical diffuser including a first layer having an electrically-conductive track formed therein, and a second layer, having the first layer resting thereon resting thereon, and having at least two electrically-conductive pillars extending across the entire thickness of the second layer formed therein. The second layer includes at least one first region located under the conductive track comprising no pillar.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

摘要： An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20170200730A1

公开(公告)日：2017-07-13

申请号：US15228236

申请日：2016-08-04

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Stephane Zoll ,  Philippe Garnier

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC分类号： H01L27/11539 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

摘要： Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US20180286878A1

公开(公告)日：2018-10-04

申请号：US15995452

申请日：2018-06-01

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Stephane Zoll ,  Philippe Garnier

IPC分类号： H01L27/11539 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/788

摘要： Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US10014308B2

公开(公告)日：2018-07-03

申请号：US15228236

申请日：2016-08-04

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Stephane Zoll ,  Philippe Garnier

IPC分类号： H01L27/105 ,  H01L27/11539 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11521

CPC分类号： H01L27/11539 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

摘要： Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.