公开(公告)号：US09412589B2

公开(公告)日：2016-08-09

申请号：US14501639

申请日：2014-09-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Philippe Garnier ,  Yves Campidelli

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02609 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract translation: 集成电路包括在SOI衬底的不同区域上的NMOS晶体管和PMOS晶体管。 每个晶体管包括栅极区域，在栅极区域的侧面上的多层横向绝缘区域，同时也在衬底上。 每个多层横向绝缘区域包括远离基板倾斜的倾斜部分。 源区和漏区在衬底上，并通过相应的多层横向绝缘区与栅极区的侧面分离。 源极和漏极区域具有靠在横向绝缘区域的倾斜部分的倾斜部分。

公开(公告)号：US20180286878A1

公开(公告)日：2018-10-04

申请号：US15995452

申请日：2018-06-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/11539 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/788

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US10014308B2

公开(公告)日：2018-07-03

申请号：US15228236

申请日：2016-08-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/105 ,  H01L27/11539 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L27/11539 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US09437498B2

公开(公告)日：2016-09-06

申请号：US14636778

申请日：2015-03-03

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Stéphane Zoll ,  Philippe Garnier ,  Olivier Gourhant ,  Vincent Joseph

IPC: H01L21/3205 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/324 ,  H01L21/033 ,  H01L21/28

CPC classification number: H01L21/823437 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/324 ,  H01L29/4966

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract translation: 一种方法是形成至少两个MOS晶体管的至少两个不同的栅极金属区域。 该方法可以包括在栅介质层上形成金属层; 以及在所述金属层上形成金属硬掩模，所述硬掩模具有不同于所述金属层的组成，并且覆盖所述金属层的第一区域并且留下所述金属层的第二区域。 该方法还可以包括对先前步骤中获得的中间结构进行扩散退火，以使硬掩模的金属原子扩散到第一区域中，以及去除硬掩模。

公开(公告)号：US20170200730A1

公开(公告)日：2017-07-13

申请号：US15228236

申请日：2016-08-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11539 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.