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公开(公告)号:US11265145B2
公开(公告)日:2022-03-01
申请号:US16281881
申请日:2019-02-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Yanis Linge , Thomas Ordas , Pierre-Yvan Liardet
Abstract: The disclosure concerns implementing, by a cryptographic circuit, a set of substitution operations of a cryptographic process involving a plurality of substitution tables. For each set of substitution operations of the cryptographic process, a series of sets of substitution operations are performed. One set of the series is a real set of substitution operations corresponding to the set of substitution operations of the cryptographic process. One or more other sets are dummy sets of substitution operations, each dummy set being based on a different permutation of said substitution tables.
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公开(公告)号:US20170250795A1
公开(公告)日:2017-08-31
申请号:US15221749
申请日:2016-07-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Thomas Ordas , Alexandre Sarafianos , Stephane Chesnais , Fabrice Marinet
CPC classification number: H04L9/002 , G06F1/04 , G06F21/72 , G06K19/07336 , G09C1/00 , H01L23/528 , H03K3/84 , H03K5/01 , H03K2005/00019 , H04K3/825 , H04K2203/32 , H04L9/003 , H04L2209/08 , H04L2209/805
Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
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公开(公告)号:US11049419B2
公开(公告)日:2021-06-29
申请号:US16186820
申请日:2018-11-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge
IPC: G09C1/00 , H03K19/003 , H04L9/00 , G06F21/75
Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.
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公开(公告)号:US10769513B2
公开(公告)日:2020-09-08
申请号:US16227525
申请日:2018-12-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , G06F21/75 , G06F21/44 , H01L23/00
Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
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公开(公告)号:US10473709B2
公开(公告)日:2019-11-12
申请号:US16125096
申请日:2018-09-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas
IPC: H01L23/00 , G01R31/12 , G06K19/073 , H01L25/065 , G01R31/317 , H01L23/538
Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
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公开(公告)号:US11218291B2
公开(公告)日:2022-01-04
申请号:US16281889
申请日:2019-02-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Thomas Ordas , Yanis Linge
Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.
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公开(公告)号:US10949572B2
公开(公告)日:2021-03-16
申请号:US16411819
申请日:2019-05-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06F21/75 , H04L9/00 , G06F30/327
Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
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公开(公告)号:US20180341788A1
公开(公告)日:2018-11-29
申请号:US15920835
申请日:2018-03-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas
IPC: G06F21/76 , G11C19/28 , H03K19/003 , H03K19/21 , H03K19/20
Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.
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公开(公告)号:US20180189624A1
公开(公告)日:2018-07-05
申请号:US15798553
申请日:2017-10-31
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , H01L23/00 , G06F21/44
CPC classification number: G06K19/07363 , G06F21/445 , G06F21/75 , G06F21/755 , H01L23/576 , H01L2224/48228
Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
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公开(公告)号:US10734329B2
公开(公告)日:2020-08-04
申请号:US15801517
申请日:2017-11-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas
IPC: H01L21/56 , H01L23/00 , H01L27/118 , H01L27/02
Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
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