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公开(公告)号：US11018644B2
公开(公告)日：2021-05-25
申请号：US16695010
申请日：2019-11-25
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： XiangSheng Li , Ru Feng Du
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US10193506B2
公开(公告)日：2019-01-29
申请号：US15377929
申请日：2016-12-13
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Ru Feng Du , Qi Yu Liu
IPC: H03F1/32 , H03G3/34 , H03F3/45 , H03F3/187 , H03F3/217 , H03F1/02 , H04R3/00 , H03F1/30 , H03F3/183 , H03F3/185 , H03F3/21
Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
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公开(公告)号：US20170093348A1
公开(公告)日：2017-03-30
申请号：US15377929
申请日：2016-12-13
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Ru Feng Du , Qi Yu Liu
CPC classification number: H03F1/3205 , H03F1/0205 , H03F1/305 , H03F3/183 , H03F3/185 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/45179 , H03F2200/03 , H03F2200/351 , H03F2203/21106 , H03F2203/45151 , H03F2203/45156 , H03G3/345 , H03G3/348 , H04R3/002
Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
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公开(公告)号：US12231102B2
公开(公告)日：2025-02-18
申请号：US18493282
申请日：2023-10-24
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： XiangSheng Li , Ru Feng Du
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US11750163B2
公开(公告)日：2023-09-05
申请号：US17200490
申请日：2021-03-12
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Ru Feng Du , Qi Yu Liu
IPC: H03F3/217 , H03G1/04 , H03K19/017 , H03K19/20 , H03K19/003 , H03G3/30 , H03K19/096
CPC classification number: H03G1/04 , H03F3/2173 , H03G3/3026 , H03K19/00323 , H03K19/01728 , H03K19/096 , H03K19/20 , H03F2200/78
Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
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Patent Agency Ranking
公开(公告)号：US10944366B2
公开(公告)日：2021-03-09
申请号：US16291971
申请日：2019-03-04
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： Ru Feng Du , XiangSheng Li
Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.
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公开(公告)号：US20140285258A1
公开(公告)日：2014-09-25
申请号：US14199773
申请日：2014-03-06
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Ru Feng Du , Qi Yu Liu
IPC: H03F3/217
CPC classification number: H03F3/2171 , H03F3/2175
Abstract: A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.
Abstract translation: D类放大器包括前置放大器，其具有被配置为接收在启动时以快速速率斜坡的放大器参考电压信号的输入。 积分器具有被配置为从前置放大器接收输入信号的第一输入和被配置为接收以较慢速率在启动时斜坡上升的积分器参考电压信号的第二输入。 调制器具有耦合到积分器的输出的输入。 调制器产生脉宽调制输出信号。 通过将缓慢斜坡信号作为积分器参考电压信号和快速斜坡信号作为放大器参考电压来控制D类放大器的工作，使得脉宽调制输出信号在占空比上呈现增加的变化 响应于积分器参考电压信号的增加的电压，并且在启动时不引入“弹出”。
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公开(公告)号：US10965263B2
公开(公告)日：2021-03-30
申请号：US16354760
申请日：2019-03-15
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Ru Feng Du , Qi Yu Liu
IPC: H03F3/217 , H03G1/04 , H03K19/017 , H03K19/20 , H03K19/003 , H03G3/30 , H03K19/096
Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
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公开(公告)号：US20200169234A1
公开(公告)日：2020-05-28
申请号：US16695010
申请日：2019-11-25
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： XiangSheng Li , Ru Feng Du
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US09667201B2
公开(公告)日：2017-05-30
申请号：US15002589
申请日：2016-01-21
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Ru Feng Du , Qi Yu Liu
CPC classification number: H03F1/523 , H03F3/183 , H03F3/185 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2200/462 , H03F2200/78 , H03F2203/45512 , H03F2203/45528 , H03F2203/45594
Abstract: A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker.
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