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Patent Agency Ranking
公开(公告)号：US11646741B2
公开(公告)日：2023-05-09
申请号：US17931043
申请日：2022-09-09
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Prashutosh Gupta , Ankit Gupta
CPC classification number: H03L7/0812 , H03L7/085
Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.
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公开(公告)号：US11451233B2
公开(公告)日：2022-09-20
申请号：US17525680
申请日：2021-11-12
Applicant: STMicroelectronics International N.V.
Inventor： Prashutosh Gupta , Ankit Gupta
Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.
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公开(公告)号：US11171619B2
公开(公告)日：2021-11-09
申请号：US16829088
申请日：2020-03-25
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Prashutosh Gupta
Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.
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公开(公告)号：US11251784B2
公开(公告)日：2022-02-15
申请号：US17193532
申请日：2021-03-05
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Anand Kumar , Prashutosh Gupta
Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.
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公开(公告)号：US11016519B2
公开(公告)日：2021-05-25
申请号：US16694028
申请日：2019-11-25
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Gupta , Nitin Gupta , Prashutosh Gupta
Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.
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