公开(公告)号：US20230280915A1

公开(公告)日：2023-09-07

申请号：US18196152

申请日：2023-05-11

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Harsh RAWAT

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: A read-modify-write operation is performed, within a single cycle of a clock signal, by: decoding an address to select a word line of a memory; applying a word line signal at a first voltage level to the selected word line; reading a current data word from a data word location in the memory; reducing the word line signal from the first voltage level to the second voltage level; performing a mathematical modify operation internally within the memory on the current data word to generate a modified data word; increasing the word line signal from the second voltage level to the first voltage level; and writing the modified data word back to the location in the memory.

公开(公告)号：US20230051672A1

公开(公告)日：2023-02-16

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh RAWAT ,  Praveen Kumar VERMA ,  Promod KUMAR ,  Christophe LECOCQ

IPC: G11C8/10 ,  G11C8/08 ,  G11C7/10 ,  G11C7/22

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

公开(公告)号：US20240363187A1

公开(公告)日：2024-10-31

申请号：US18635569

申请日：2024-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Christophe LECOCQ ,  Yagnesh Dineshbhai VADERIYA ,  Anuj DHILLON ,  Cedric ESCALLIER ,  Harsh RAWAT ,  Kedar Janardan DHORI

IPC: G11C29/46 ,  G11C29/02 ,  G11C29/32

CPC classification number: G11C29/46 ,  G11C29/022 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

公开(公告)号：US20240331767A1

公开(公告)日：2024-10-03

申请号：US18614460

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Anuj DHILLON

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.

公开(公告)号：US20230015002A1

公开(公告)日：2023-01-19

申请号：US17852677

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Praveen Kumar VERMA

IPC: G11C11/419 ,  G11C11/412

Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

公开(公告)号：US20250054528A1

公开(公告)日：2025-02-13

申请号：US18929840

申请日：2024-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

IPC: G11C8/20 ,  G11C11/418

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

公开(公告)号：US20230135708A1

公开(公告)日：2023-05-04

申请号：US17965243

申请日：2022-10-13

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA

IPC: G06F3/06

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

公开(公告)号：US20230050783A1

公开(公告)日：2023-02-16

申请号：US17861384

申请日：2022-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Harsh RAWAT

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

公开(公告)号：US20230018420A1

公开(公告)日：2023-01-19

申请号：US17853026

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

IPC: G11C8/20 ,  G11C11/418

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

公开(公告)号：US20250054529A1

公开(公告)日：2025-02-13

申请号：US18930022

申请日：2024-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

IPC: G11C8/20 ,  G11C11/418

Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.