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    Data sampler circuit
    1.
    发明授权
    Data sampler circuit 有权
    数据采样电路

    公开(公告)号：US09524798B2

    公开(公告)日：2016-12-20

    申请号：US13960213

    申请日：2013-08-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Sajal Kumar Mandal

    IPC: G11C27/02

    CPC classification number: G11C27/026

    Abstract: A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.

    Abstract translation: 电路包括：第一电路级，被配置为在采样时钟的第一逻辑状态下对差分输入信号进行采样，并在采样时钟的第二逻辑状态下重新产生采样的差分输入信号，以输出第一再生的差分信号; 第二电路级，被配置为在采样时钟的第二逻辑状态下放大第一再生差分信号，以输出放大的差分信号; 以及第三电路级，被配置为在采样时钟的第一逻辑状态下再生放大的差分信号，以输出第二再生的差分信号。

    Oversampling CDR which compensates frequency difference without elasticity buffer
    3.
    发明授权
    Oversampling CDR which compensates frequency difference without elasticity buffer 有权
    过采样CDR，补偿频率差，无弹性缓冲

    公开(公告)号：US09356770B2

    公开(公告)日：2016-05-31

    申请号：US14231499

    申请日：2014-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhishek Chowdhary ,  Vivek Uppal ,  Alok Kaushik ,  Sajal Kumar Mandal ,  Tapas Nandy ,  Sanjeev Chopra

    IPC: H04L7/00 ,  H04L7/033 ,  H03L7/091 ,  H04L25/03

    CPC classification number: H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

    Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

    Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。

    Power-on-Reset and Supply Brown Out Detection Circuit with Programmability
    5.
    发明申请
    Power-on-Reset and Supply Brown Out Detection Circuit with Programmability 审中-公开
    上电复位和供电欠压检测电路具有可编程性

    公开(公告)号：US20150236689A1

    公开(公告)日：2015-08-20

    申请号：US14675533

    申请日：2015-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Pralay Mandal ,  Sajal Kumar Mandal

    IPC: H03K17/22

    CPC classification number: H03K17/223 ,  G06F1/28

    Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

    Abstract translation: 提出了一种低功率宽带上电复位（PoR）和电源欠压检测电路，提出了一种精确控制PoR跳变点和滞后电压的技术。 PoR电路包括具有不对称上升和下降延迟的CMOS电路，用于监视宽带电源电压瞬变，包括电源欠压。 作为非带隙和非比较器的电路，它消耗了非常小的功率和Si面积。

    Power-on-Reset and Supply Brown Out Detection Circuit with Programmability
    6.
    发明申请
    Power-on-Reset and Supply Brown Out Detection Circuit with Programmability 有权
    上电复位和供电欠压检测电路具有可编程性

    公开(公告)号：US20140111258A1

    公开(公告)日：2014-04-24

    申请号：US13659722

    申请日：2012-10-24

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Pralay Mandal ,  Sajal Kumar Mandal

    IPC: H03K17/22

    CPC classification number: H03K17/223 ,  G06F1/28

    Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

    Abstract translation: 提出了一种低功率宽带上电复位（PoR）和电源欠压检测电路，提出了一种精确控制PoR跳变点和滞后电压的技术。 PoR电路包括具有不对称上升和下降延迟的CMOS电路，用于监视宽带电源电压瞬变，包括电源欠压。 作为非带隙和非比较器的电路，它消耗了非常小的功率和Si面积。

    OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER
    8.
    发明申请
    OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER 有权
    补偿没有弹性缓冲区的频率差异

    公开(公告)号：US20150280898A1

    公开(公告)日：2015-10-01

    申请号：US14231499

    申请日：2014-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhishek Chowdhary ,  Vivek Uppal ,  Alok Kaushik ,  Sajal Kumar Mandal ,  Tapas Nandy ,  Sanjeev Chopra

    IPC: H04L7/00 ,  H04L7/033 ,  H03L7/091

    CPC classification number: H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

    Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

    Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。

    Power-on-reset and supply brown out detection circuit with programmability
    9.
    发明授权
    Power-on-reset and supply brown out detection circuit with programmability 有权
    上电复位并提供具有可编程性的欠压检测电路

    公开(公告)号：US09018989B2

    公开(公告)日：2015-04-28

    申请号：US13659722

    申请日：2012-10-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Pralay Mandal ,  Sajal Kumar Mandal

    IPC: H03L7/00 ,  G06F1/28 ,  H03K17/22

    CPC classification number: H03K17/223 ,  G06F1/28

    Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

    Abstract translation: 提出了一种低功率宽带上电复位（PoR）和电源欠压检测电路，提出了一种精确控制PoR跳变点和滞后电压的技术。 PoR电路包括具有不对称上升和下降延迟的CMOS电路，用于监视宽带电源电压瞬变，包括供电褐变。 作为非带隙和非比较器的电路，它消耗了非常小的功率和Si面积。

    Generating a root of an open-loop freqency response that tracks an opposite root of the frequency response
    10.
    发明授权
    Generating a root of an open-loop freqency response that tracks an opposite root of the frequency response 有权
    生成跟踪频率响应的相反根的开环频率响应的根

    公开(公告)号：US09256233B2

    公开(公告)日：2016-02-09

    申请号：US13915828

    申请日：2013-06-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Pralay Mandal ,  Sajal Kumar Mandal

    IPC: G05F1/575 ,  G05F1/445

    CPC classification number: G05F1/445 ,  G05F1/575

    Abstract: In an embodiment, an electronic includes a feedback-coupled circuit stage and a compensation circuit stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that a combination of the compensation and feedback-coupled stages has a frequency response including a first root and an opposite second root that depend on the load. For example, an embodiment of such an electronic circuit may be a low-dropout (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator. The regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that is designed such that the frequency response of the regulator includes a zero that tracks a non-dominant output pole of the regulator so that the output pole does not adversely affect the stability of the regulator.

    Abstract translation: 在一个实施例中，电子器件包括反馈耦合电路级和补偿电路级。 反馈耦合级被配置为驱动负载，并且补偿级耦合到反馈耦合级，使得补偿和反馈耦合级的组合具有包括第一根和相对的第二根的频率响应， 取决于负载。 例如，这种电子电路的实施例可以是缺少大输出电容的低压差（LDO）电压调节器，用于形成用于稳定调节器的主极。 调节器包括产生和调节输出电压的反馈耦合级，并且包括被设计为使得调节器的频率响应包括跟踪调节器的非主导输出极的零的补偿级，使得输出 极不会不利地影响调节器的稳定性。

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