公开(公告)号：US20190331733A1

公开(公告)日：2019-10-31

申请号：US16505174

申请日：2019-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US20230042541A1

公开(公告)日：2023-02-09

申请号：US17443556

申请日：2021-07-27

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/22 ,  G11C7/10 ,  G11C29/36 ,  G11C29/14

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

公开(公告)号：US20200333399A1

公开(公告)日：2020-10-22

申请号：US16387809

申请日：2019-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Shiv Kumar VATS ,  HIMANSHU

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/3183

Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.

公开(公告)号：US20230128466A1

公开(公告)日：2023-04-27

申请号：US17510602

申请日：2021-10-26

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA ,  Tripti GUPTA

IPC: G01R31/3177 ,  G06F1/28 ,  G01R31/317

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

公开(公告)号：US20200064405A1

公开(公告)日：2020-02-27

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/27 ,  G06F11/267

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

公开(公告)号：US20250070785A1

公开(公告)日：2025-02-27

申请号：US18236038

申请日：2023-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Ajay Kumar DIMRI

IPC: H03L7/08 ,  G01R31/28 ,  H03K3/037 ,  H03K19/20

Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.

公开(公告)号：US20240296899A1

公开(公告)日：2024-09-05

申请号：US18661914

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/10 ,  G11C7/22 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  H03K19/20

CPC classification number: G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

公开(公告)号：US20200125149A1

公开(公告)日：2020-04-23

申请号：US16162543

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Srinivas DHULIPALLA ,  Sandip ATAL

IPC: G06F1/24 ,  H03K19/00 ,  H03K17/22 ,  G06F1/32 ,  G01R31/319

Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.