公开(公告)号：US20010033245A1

公开(公告)日：2001-10-25

申请号：US09773300

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar ,  Luigi Pascucci

IPC: H03M001/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract translation: 适用于更广泛应用的多用途存储器件，无论是要求以随机存取（如在标准存储器中）或具有顺序或突发型访问的同步顺序模式的异步模式中的数据读取，都能够识别 访问模式和微处理器当前需要的读取模式。 存储器设备将其内部电路作为这种识别的功能进行自我调整，以便以所请求的模式读取数据，而不需要使用额外的外部控制信号和/或暗示相对于访问时间和读取时间的惩罚 对于相同的制造技术和现有技术设计的那些，可以通过专门为一种或另一种操作模式设计的存储器件来实现。

公开(公告)号：US20020087817A1

公开(公告)日：2002-07-04

申请号：US09977561

申请日：2001-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Tomaiuolo ,  Salvatore Nicosia ,  Luigi Pascucci

IPC: G06F012/00

CPC classification number: G11C7/1033 ,  G11C7/1045

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract translation: 多用途隔行存储器件具有两种不同的同步和异步模式。 存储器使用用于检测地址转换的电路，用作系统的同步时钟，以通过使当前输入的外部地址与存储在地址计数器中的当前输入的外部地址进行比较来使存储器件的控制电路识别所需的访问模式 的两行记忆体。 存储装置包括用于输出数据的缓冲器。 缓冲器包括用于将输出节点预充电到对应于两个可能逻辑状态的电压之间的中间电压的电路，从而降低噪声并改善传输时间。

公开(公告)号：US20010034819A1

公开(公告)日：2001-10-25

申请号：US09774542

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC: G06F012/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract translation: 具有交错数据路径的交错存储器包括被分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。

公开(公告)号：US20040218440A1

公开(公告)日：2004-11-04

申请号：US10789443

申请日：2004-02-27

Applicant: STMicroelectronics S.r.I.

Inventor： Promod Kumar ,  Francesco Tomaiuolo ,  Pierpaolo Nicosia ,  Luca Giuseppe De Ambroggi ,  Francesco Pipitone

IPC: G11C011/34

CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405

Abstract: An effective Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. The architecture provides for executing test routines internally without involving any external complex or expensive test equipment to control the test program. The processes are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided). Managing test routines by an internal process permits the device architecture to be transparent from a tester point of view, by purposely creating a standard interface with a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

Abstract translation: 通过扩展嵌入在FLASH EPROM存储器件和集成测试结构中的微控制器的功能来实现有效的电晶片分级（EWS）流程。 该架构提供在内部执行测试例程，而不涉及任何外部复杂或昂贵的测试设备来控制测试程序。 这些过程由板载微控制器执行（可能是从嵌入式ROM或从提供的GLOBAL CACHE读取）。 通过内部进程来管理测试例程允许设备架构从测试人员的角度来看是透明的，目的是通过一组定义的命令和指令来创建标准接口，由板载微控制器解释并在内部执行。