公开(公告)号：US20030122693A1

公开(公告)日：2003-07-03

申请号：US10325707

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: H03M005/00

CPC classification number: H03M5/00

Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

Abstract translation: 二进制编码电路用于将至少第一和第二二进制输入信号转换成包括至少第一和第二二进制输出信号的输出代码。 电路可以包括互连的至少一个第一选择电路和至少一个第二选择电路，并且包括可以被激活/去激活的晶体管，即根据二进制输入信号导通/不导通的晶体管。 该电路使得可以生成表示同时被断言的二进制输入信号的二进制数的二进制代码。 例如，编码电路可以用作静态计数器。

公开(公告)号：US20020067640A1

公开(公告)日：2002-06-06

申请号：US09972769

申请日：2001-10-05

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C016/04

CPC classification number: G11C7/1042 ,  G11C8/12 ,  G11C16/08

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract translation: 一种半导体存储器架构，其具有两个存储体，每个存储体各自包含相应的存储器位置，并且对于每个存储体，各个电路用于选择存储体的位置以及用于读取包含在存储体的选定位置中的数据的相应电路，转移结构 由与存储体相关联的读取电路读取的数据读取到存储器的数据输出端，存在一次分配给一个存储体的单个数据传输结构，其中包括存储用于存储最近的数据读取的存储器 读取电路和输出驱动器电路被选择性地激活，以将寄存器的内容传送到存储器的数据输出端，对于每个存储体，具有用于存储器位置的顺序扫描的寻址结构 ，可操作地连接到相应的电路以选择存储体的位置。

公开(公告)号：US20040008539A1

公开(公告)日：2004-01-15

申请号：US10434395

申请日：2003-05-07

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C016/04 ,  G11C029/00

CPC classification number: G11C14/00

Abstract: A non-volatile latch circuit includes a first, volatile information-storage element; a second, non-volatile information-storage element electrically programmable and associated with the first element; first circuit means activatable for operatively coupling the second element to the first element, the first circuit means being activated for loading into the first element an information stored in the second element. The circuit additionally includes second circuit means associated with the first element for setting the first element in a select state; third circuit means associated with the second element and driven by the first element for selectively enabling the programming of the second element depending on the state of the first element.

Abstract translation: 非易失性锁存电路包括第一易失性信息存储元件; 电可编程并与第一元件相关联的第二非易失性信息存储元件; 第一电路装置可激活以将第二元件可操作地耦合到第一元件，第一电路装置被激活以将第一元件中存储的信息加载到第一元件中。 电路还包括与第一元件相关联的用于将第一元件设置在选择状态的第二电路装置; 与第二元件相关联并由第一元件驱动的第三电路装置，用于根据第一元件的状态选择性地启用第二元件的编程。

公开(公告)号：US20020087817A1

公开(公告)日：2002-07-04

申请号：US09977561

申请日：2001-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Tomaiuolo ,  Salvatore Nicosia ,  Luigi Pascucci

IPC: G06F012/00

CPC classification number: G11C7/1033 ,  G11C7/1045

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract translation: 多用途隔行存储器件具有两种不同的同步和异步模式。 存储器使用用于检测地址转换的电路，用作系统的同步时钟，以通过使当前输入的外部地址与存储在地址计数器中的当前输入的外部地址进行比较来使存储器件的控制电路识别所需的访问模式 的两行记忆体。 存储装置包括用于输出数据的缓冲器。 缓冲器包括用于将输出节点预充电到对应于两个可能逻辑状态的电压之间的中间电压的电路，从而降低噪声并改善传输时间。

公开(公告)号：US20010033245A1

公开(公告)日：2001-10-25

申请号：US09773300

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar ,  Luigi Pascucci

IPC: H03M001/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract translation: 适用于更广泛应用的多用途存储器件，无论是要求以随机存取（如在标准存储器中）或具有顺序或突发型访问的同步顺序模式的异步模式中的数据读取，都能够识别 访问模式和微处理器当前需要的读取模式。 存储器设备将其内部电路作为这种识别的功能进行自我调整，以便以所请求的模式读取数据，而不需要使用额外的外部控制信号和/或暗示相对于访问时间和读取时间的惩罚 对于相同的制造技术和现有技术设计的那些，可以通过专门为一种或另一种操作模式设计的存储器件来实现。

公开(公告)号：US20030235100A1

公开(公告)日：2003-12-25

申请号：US10426924

申请日：2003-04-29

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C007/00

CPC classification number: G11C16/3427 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

Abstract: An NROM memory device, wherein the memory cells are provided with charge storage regions of insulating material, such as silicon nitride. The memory device includes a row decoder comprising a plurality of drivers; during programming, a first driver supplies a first voltage having a first value to a selected wordline, while the other drivers are configured so as to supply a second voltage having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region.

Abstract translation: 一种NROM存储器件，其中存储单元设置有诸如氮化硅的绝缘材料的电荷存储区域。 存储装置包括行解码器，其包括多个驱动器; 在编程期间，第一驱动器向所选择的字线提供具有第一值的第一电压，而其他驱动器被配置为将具有低于第一值的第二非零值的第二电压提供给其它字线 。 因此，取消选择的单元的栅极 - 漏极电压降降低，并且因此连接到所选位线的取消选择的单元的寄生擦除减少。 因此，由于注入到电荷存储区域的电荷减少，存储器件的可靠性显着提高并且寿命延长。

公开(公告)号：US20030197217A1

公开(公告)日：2003-10-23

申请号：US10372044

申请日：2003-02-20

Applicant: STMicroelectronics S.r.I

Inventor： Luigi Pascucci

IPC: H01L021/336 ,  H01L029/788

CPC classification number: H01L29/7923 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28282

Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element capacitively coupled to a memory cell channel for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions are formed in a semiconductor layer and define a channel region there between; at least one of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer. The dielectric layer has a reduced thickness in a portion thereof near the at least one programming electrode.

Abstract translation: 通过将通道热电子注入到电容耦合到存储单元通道的电荷存储元件来编程的电可编程存储单元，用于根据存储的电荷量来调制其电导率。 第一和第二间隔开的电极区域形成在半导体层中并在其间限定沟道区域; 第一和第二电极区域中的至少一个用作存储单元的编程电极。 控制电极电容耦合到电荷存储元件。 电荷存储元件放置在通道上，从第一至第二电极区域基本上延伸，并通过电介质层与沟道区分离。 电介质层在其至少一个编程电极附近的部分中具有减小的厚度。