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公开(公告)号：US20140104666A1
公开(公告)日：2014-04-17
申请号：US14043547
申请日：2013-10-01
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Gabriele MINOIA , Salvatore Galeone , Enrico Stefano Temporiti Milani
IPC: G02F1/01
CPC classification number: G02F1/0121 , G02F1/225 , G02F2201/126 , H03K19/018521 , H03K19/018528
Abstract: A relatively high-speed, high-efficiency CMOS two branch driver core that may operate under relatively low supply voltage may include thin oxide CMOS transistors configured to generate rail-to-rail output swings larger than twice a supply voltage and without exceeding safe operating area limits. Each of the two branches may include two stacked CMOS inverter pairs configured to drive a respective load capacitance coupled between respective CMOS inverter outputs, in phase opposition to the other branch. A pre-driver circuit input with a differential modulating signal may output two synchronous differential voltage drive signals of a swing of half of the supply voltage and DC-shifted by half of the supply voltage with respect to each other and that may be applied to the respective CMOS inverter inputs of the two branches.
Abstract translation: 可以在相对低的电源电压下工作的相对高速，高效率的CMOS两分支驱动器核心可以包括薄氧化物CMOS晶体管，其被配置为产生大于电源电压两倍的轨至轨输出摆幅，并且不超过安全操作区域 限制 两个分支中的每一个可以包括两个堆叠的CMOS反相器对，其被配置为驱动耦合在各个CMOS反相器输出之间的相应负载电容，与另一个分支相反。 具有差分调制信号的预驱动器电路输入可以输出两个同步差分电压驱动信号，该两个同步差分电压驱动信号是电源电压的一半的摆幅，并相对于彼此直流偏移电源电压的一半，并且可以施加到 相应的CMOS反相器输入的两个分支。
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公开(公告)号：US09018984B2
公开(公告)日：2015-04-28
申请号：US14160921
申请日：2014-01-22
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Zuffada , Enrico Stefano Temporiti Milani , Antonio Fincato
IPC: H03K17/10 , H03K3/012 , H03K19/0175 , H03K17/0416 , H03F3/45
CPC classification number: H03K3/012 , G02F1/0121 , H03F3/4508 , H03F2203/45318 , H03F2203/45394 , H03K17/0416 , H03K17/10 , H03K19/0175
Abstract: An electrical-optical modulator may function at high data rates and may be realized in comparably low cost silicon base technology, typically in BJT, BiCMOS or CMOS technologies. The output signal path may include a high transition frequency BJT and by using an active load constituted by a MOS driven by an inverted version of the modulating signal that drives the BJT, the falling edge of the output signal is sped up.
Abstract translation: 电光调制器可以以高数据速率工作，并且可以通过比较低成本的硅基技术实现，通常在BJT，BiCMOS或CMOS技术中。 输出信号路径可以包括高转换频率BJT，并且通过使用由驱动BJT的调制信号的反转版本驱动的MOS构成的有源负载，输出信号的下降沿被加快。
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公开(公告)号：US09229250B2
公开(公告)日：2016-01-05
申请号：US14043547
申请日：2013-10-01
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Gabriele Minoia , Salvatore Galeone , Enrico Stefano Temporiti Milani
IPC: H03K19/0175 , G02F1/01 , H03K19/0185 , G02F1/225
CPC classification number: G02F1/0121 , G02F1/225 , G02F2201/126 , H03K19/018521 , H03K19/018528
Abstract: A relatively high-speed, high-efficiency CMOS two branch driver core that may operate under relatively low supply voltage may include thin oxide CMOS transistors configured to generate rail-to-rail output swings larger than twice a supply voltage and without exceeding safe operating area limits. Each of the two branches may include two stacked CMOS inverter pairs configured to drive a respective load capacitance coupled between respective CMOS inverter outputs, in phase opposition to the other branch. A pre-driver circuit input with a differential modulating signal may output two synchronous differential voltage drive signals of a swing of half of the supply voltage and DC-shifted by half of the supply voltage with respect to each other and that may be applied to the respective CMOS inverter inputs of the two branches.
Abstract translation: 可以在相对低的电源电压下工作的相对高速，高效率的CMOS两分支驱动器核心可以包括薄氧化物CMOS晶体管，其被配置为产生大于电源电压两倍的轨至轨输出摆幅，并且不超过安全操作区域 限制 两个分支中的每一个可以包括两个堆叠的CMOS反相器对，其被配置为驱动耦合在各个CMOS反相器输出之间的相应负载电容，与另一个分支相反。 具有差分调制信号的预驱动器电路输入可以输出两个同步差分电压驱动信号，该两个同步差分电压驱动信号是电源电压的一半的摆幅，并相对于彼此直流偏移电源电压的一半，并且可以施加到 相应的CMOS反相器输入的两个分支。
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公开(公告)号：US08989601B2
公开(公告)日：2015-03-24
申请号：US14043375
申请日：2013-10-01
Applicant: STMicroelectronics S.R.L.
Inventor： Enrico Stefano Temporiti Milani , Matteo Repossi , Daniele Baldi
CPC classification number: H04B10/5051 , G02F1/0121 , G02F1/025 , G02F2201/20 , H04B10/5053 , H04B10/5055
Abstract: A modular hub driver architecture may include a multi-delay block configured to provide an enhanced delay match among N distinct stages of a distributed modulating electro-optical interface core. The electro-optical multi-core modulator driver may include an input impedance matching stage and a pre-conditioning circuit configured to generate a number M, an integer divisor of N, of delayed replicas of an electrical modulating signal. The electro-optical multi-core modulator may include an array of M launch buffers of the replica signals, and an array of M multi-delay blocks, each including delay circuit modules differently cascaded on distinct signal paths, and configured to receive, at respective inputs, the M replica signals and to output N/M differently delayed replicas of the input signals, each driving a correspondent output stage of one on the N electro-optical interface cores.
Abstract translation: 模块化集线器驱动器架构可以包括被配置为在分布式调制电光接口核心的N个不同阶段之间提供增强的延迟匹配的多延迟块。 电光多核调制器驱动器可以包括输入阻抗匹配级和预处理电路，其被配置为产生电调制信号的延迟复制的数字M，N的整数除数。 电光多核调制器可以包括复制信号的M个启动缓冲器的阵列，以及M个多延迟块的阵列，每个M多延迟块包括在不同的信号路径上不同级联的延迟电路模块，并且被配置为在相应的 输入，M个复制信号，并输出N / M个输入信号的不同延迟的副本，每个在N个电光接口核心上驱动一个对应的输出级。
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公开(公告)号：US11079232B2
公开(公告)日：2021-08-03
申请号：US16511152
申请日：2019-07-15
Applicant: STMicroelectronics S.r.l.
IPC: G01C19/72
Abstract: A device includes an optical resonator having four ports including a first port, a second port, a third port, and a fourth port. A first electronic circuit is configured to calculate a first information representative of a power difference between optical signals supplied by two of the four ports. A method of operating a device is also disclosed.
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Patent Agency Ranking
公开(公告)号：US20200025569A1
公开(公告)日：2020-01-23
申请号：US16511152
申请日：2019-07-15
Applicant: STMicroelectronics S.r.l.
IPC: G01C19/72
Abstract: A device includes an optical resonator having four ports including a first port, a second port, a third port, and a fourth port. A first electronic circuit is configured to calculate a first information representative of a power difference between optical signals supplied by two of the four ports. A method of operating a device is also disclosed.
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公开(公告)号：US09391708B2
公开(公告)日：2016-07-12
申请号：US14714582
申请日：2015-05-18
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Antonio Fincato , Salvatore Mario Rotolo , Enrico Stefano Temporiti Milani , Maurizio Zuffada
CPC classification number: H04B10/40 , H04B10/503 , H04B10/70 , H04B10/801 , H05K3/30 , Y10T29/49131
Abstract: An intra-board chip-to-chip optical communications system has a high bit rate and high data throughput based on the use of a silicon photonic interposer. The system includes a multi-substrate electro-optical structure for communications with CMOS and/or BiCMOS IC chips of a PCB. The structure includes a multi-chip module primary substrate mounted over the supporting PCB. The multi-chip module primary substrate implements high frequency electrical interconnections between transceiver circuit chips, mounted on the silicon photonic interposer, and the IC chips.
Abstract translation: 基于硅光子插入器的使用，板内芯片到芯片的光通信系统具有高比特率和高数据吞吐量。 该系统包括用于与PCB的CMOS和/或BiCMOS IC芯片通信的多基板电光结构。 该结构包括安装在支撑PCB上的多芯片模块主要基板。 多芯片模块主要基板在安装在硅光子插入器上的收发器电路芯片和IC芯片之间实现高频电互连。
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公开(公告)号：US20150341119A1
公开(公告)日：2015-11-26
申请号：US14714582
申请日：2015-05-18
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Antonio FINCATO , Salvatore Mario Rotolo , Enrico Stefano Temporiti Milani , Maurizio Zuffada
CPC classification number: H04B10/40 , H04B10/503 , H04B10/70 , H04B10/801 , H05K3/30 , Y10T29/49131
Abstract: An intra-board chip-to-chip optical communications system has a high bit rate and high data throughput based on the use of a silicon photonic interposer. The system includes a multi-substrate electro-optical structure for communications with CMOS and/or BiCMOS IC chips of a PCB. The structure includes a multi-chip module primary substrate mounted over the supporting PCB. The multi-chip module primary substrate implements high frequency electrical interconnections between transceiver circuit chips, mounted on the silicon photonic interposer, and the IC chips.
Abstract translation: 基于硅光子插入器的使用，片内芯片到芯片的光通信系统具有高比特率和高数据吞吐量。 该系统包括用于与PCB的CMOS和/或BiCMOS IC芯片通信的多基板电光结构。 该结构包括安装在支撑PCB上的多芯片模块主要基板。 多芯片模块主要基板在安装在硅光子插入器上的收发器电路芯片和IC芯片之间实现高频电互连。
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公开(公告)号：US08981853B2
公开(公告)日：2015-03-17
申请号：US13868647
申请日：2013-04-23
Applicant: STMicroelectronics S.R.L.
CPC classification number: H03F3/45071 , H03F3/08 , H03F3/087 , H03F3/45183
Abstract: A differential or pseudo-differential TIA includes an auxiliary differential amplifier input transistor pair cross-coupled to the output nodes to cancel undesired output signal components. The advantages of a classical differential topology are retained while performance at a high data rate is significantly improved.
Abstract translation: 差分或伪差分TIA包括交叉耦合到输出节点的辅助差分放大器输入晶体管对，以消除不期望的输出信号分量。 保留经典差分拓扑的优点，同时在高数据速率下的性能得到显着改善。
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公开(公告)号：US08907729B2
公开(公告)日：2014-12-09
申请号：US13864739
申请日：2013-04-17
Applicant: STMicroelectronics S.R.L.
IPC: H03F3/08
CPC classification number: H03F3/45076 , H03F3/087 , H04B10/693
Abstract: The differential trans-impedance amplifier uses trans-resistance(s) connected between the input nodes of a first differential amplifier, to implement a trans-impedance differential amplifier in a differential fashion and has two identical resistances, each connected between the photodiode and a respective DC voltage rail of a common bias network of the photodiode adapted to reverse bias the photodiode. The biasing resistances may be much larger than the trans-resistance(s) to prevent drawing any significant signal current from the photodiode. The amplifier may retain the advantages of a classical differential topology while effectively overcoming drawbacks that arise in high data rate applications.
Abstract translation: 差分跨阻放大器使用连接在第一差分放大器的输入节点之间的反电阻，以差分方式实现跨阻抗差分放大器，并具有两个相同的电阻，每个电阻连接在光电二极管和相应的 适用于反射偏置光电二极管的光电二极管的公共偏置网络的直流电压轨。 偏置电阻可能比跨阻抗大得多，以防止从光电二极管引起任何有效的信号电流。 放大器可以保留经典差分拓扑的优点，同时有效克服在高数据速率应用中出现的缺点。
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