公开(公告)号：US20240030214A1

公开(公告)日：2024-01-25

申请号：US18480310

申请日：2023-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon PARK ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

公开(公告)号：US12237308B2

公开(公告)日：2025-02-25

申请号：US18400497

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-Woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US20240234374A9

公开(公告)日：2024-07-11

申请号：US18400497

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-Woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US11282792B2

公开(公告)日：2022-03-22

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20240136329A1

公开(公告)日：2024-04-25

申请号：US18400497

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-Woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US11776916B2

公开(公告)日：2023-10-03

申请号：US17199703

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon Park ,  Young Min Lee ,  Dae-Woo Kim ,  Hyuek Jae Lee

IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US12261164B2

公开(公告)日：2025-03-25

申请号：US18480310

申请日：2023-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

公开(公告)号：US11798929B2

公开(公告)日：2023-10-24

申请号：US17381985

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Hyuekjae Lee ,  Taehun Kim

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

公开(公告)号：US20220165722A1

公开(公告)日：2022-05-26

申请号：US17381985

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon PARK ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.