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公开(公告)号：US20240086153A1
公开(公告)日：2024-03-14
申请号：US18467521
申请日：2023-09-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungmeen MYUNG , Dong-Jin CHANG , Jaehyuk LEE , Daekun YOON , Seok Ju YUN
CPC classification number: G06F7/5443 , G06F7/405
Abstract: A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees according to an enable signal provided to the tristate logic circuits, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the 1-bit Wallace trees by a shift operation based on a clock signal.
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公开(公告)号：US20240069867A1
公开(公告)日：2024-02-29
申请号：US18351039
申请日：2023-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Jaehyuk LEE , Seungchul JUNG , Soon-Wan KWON , Sungmeen MYUNG , Daekun YOON , Dong-Jin CHANG
CPC classification number: G06F7/523 , G06F7/501 , G06F7/5443 , G11C7/109
Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.
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Patent Agency Ranking
公开(公告)号：US20250013714A1
公开(公告)日：2025-01-09
申请号：US18764855
申请日：2024-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehyuk LEE , Dong-Jin CHANG , Sungmeen MYUNG , Daekun YOON , Seok Ju YUN
IPC: G06F17/15
Abstract: A processor-implemented method includes receiving an input vector comprising a plurality of channels, performing a first convolution operation by allocating first chunks, obtained by dividing the input vector, to a plurality of first in-memory computing (IMC) macros, and performing a second convolution operation by allocating second chunks obtained by dividing a result of the first convolution operation to a plurality of second IMC macros.
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公开(公告)号：US20240103809A1
公开(公告)日：2024-03-28
申请号：US18139567
申请日：2023-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jin CHANG , Soon-Wan KWON , Seok Ju YUN , Jaehyuk LEE , Sungmeen MYUNG , Daekun YOON
CPC classification number: G06F7/507 , G06F7/504 , G06F7/5443
Abstract: Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.
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公开(公告)号：US20240241694A1
公开(公告)日：2024-07-18
申请号：US18355046
申请日：2023-07-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daekun YOON , Soon-Wan KWON , Seok Ju YUN , Jaehyuk LEE , Dong-Jin CHANG
CPC classification number: G06F7/5443 , G06F7/501 , G11C7/1012
Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.
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公开(公告)号：US20240094988A1
公开(公告)日：2024-03-21
申请号：US18117597
申请日：2023-03-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jin CHANG , Sungmeen MYUNG , Jaehyuk LEE , Daekun YOON , Seok Ju YUN
CPC classification number: G06F7/5443 , G06F7/405
Abstract: A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.
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公开(公告)号：US20240028298A1
公开(公告)日：2024-01-25
申请号：US18185461
申请日：2023-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehyuk LEE , Seok Ju YUN , Dong-Jin CHANG , Sungmeen MYUNG , Daekun YOON
IPC: G06F7/544 , G11C11/412 , G11C11/418 , G11C11/419
CPC classification number: G06F7/5443 , G11C11/412 , G11C11/418 , G11C11/419
Abstract: A memory device performs a multiplication operation using a multiplying cell including a memory cell and a switching element, in which the memory cell includes a pair of inverters connected to each other in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and has a set weight; and the switching element is connected to an output end of the memory cell and configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the weight.
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