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公开(公告)号:US20240177768A1
公开(公告)日:2024-05-30
申请号:US18350416
申请日:2023-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seungchul JUNG , Seok Ju YUN , Soon-Wan KWON
IPC: G11C11/412 , H03K19/20 , H03K19/21
CPC classification number: G11C11/412 , H03K19/20 , H03K19/215
Abstract: An apparatus includes a static random access memory (SRAM) cell including a first inverter and a second inverter, and a third inverter including a first inverter transistor and a second inverter transistor. An output terminal of the first inverter is connected to a source terminal of the second inverter transistor.
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公开(公告)号:US20170201281A1
公开(公告)日:2017-07-13
申请号:US15214784
申请日:2016-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: SeongJoong KIM , Joonseong KANG , Seok Ju YUN , Young Jun HONG
CPC classification number: H04B1/16 , H03J3/20 , H03J7/065 , H03J2200/40 , H03L7/0991 , H04B1/1027 , H04B2001/1072
Abstract: A frequency tuning apparatus includes: a frequency tuner configured to tune an oscillation frequency of an oscillator based on target information extracted from a mapping table in correspondence to a target frequency, and oscillation information collected from the oscillator; and a frequency compensator configured to compensate for a compensation error between the tuned oscillation frequency and the target frequency based on an offset table.
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公开(公告)号:US20240419628A1
公开(公告)日:2024-12-19
申请号:US18512788
申请日:2023-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyungwoo LEE , Soon-Wan KWON , Seok Ju YUN
Abstract: Provided are a digital signal processor (DSP) and an electronic device using the same. The DSP includes: a first function unit (FU) having a non-IMC (in-memory computing) operation architecture using an operation unit; a second FU having an IMC architecture using a memory cell array; and a register file used by the first FU and the second FU.
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公开(公告)号:US20240241694A1
公开(公告)日:2024-07-18
申请号:US18355046
申请日:2023-07-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Daekun YOON , Soon-Wan KWON , Seok Ju YUN , Jaehyuk LEE , Dong-Jin CHANG
CPC classification number: G06F7/5443 , G06F7/501 , G11C7/1012
Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.
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公开(公告)号:US20240094988A1
公开(公告)日:2024-03-21
申请号:US18117597
申请日:2023-03-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Jin CHANG , Sungmeen MYUNG , Jaehyuk LEE , Daekun YOON , Seok Ju YUN
CPC classification number: G06F7/5443 , G06F7/405
Abstract: A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.
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公开(公告)号:US20240028298A1
公开(公告)日:2024-01-25
申请号:US18185461
申请日:2023-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyuk LEE , Seok Ju YUN , Dong-Jin CHANG , Sungmeen MYUNG , Daekun YOON
IPC: G06F7/544 , G11C11/412 , G11C11/418 , G11C11/419
CPC classification number: G06F7/5443 , G11C11/412 , G11C11/418 , G11C11/419
Abstract: A memory device performs a multiplication operation using a multiplying cell including a memory cell and a switching element, in which the memory cell includes a pair of inverters connected to each other in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and has a set weight; and the switching element is connected to an output end of the memory cell and configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the weight.
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公开(公告)号:US20230170026A1
公开(公告)日:2023-06-01
申请号:US17880849
申请日:2022-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Ju YUN , Daekun YOON , Sang Joon KIM , Seungchul JUNG
CPC classification number: G11C16/102 , G11C16/32 , G11C16/20 , G11C29/52
Abstract: Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.
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公开(公告)号:US20210194519A1
公开(公告)日:2021-06-24
申请号:US16930445
申请日:2020-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Ju YUN , Joonseong KANG
Abstract: A communication apparatus and a communication method are provided. The communication apparatus includes an antenna configured to receive a wireless signal, an oscillator driven by a driving current and configured to generate an oscillating signal based on the wireless signal, a measurer configured to measure an oscillation degree of the oscillating signal, and an accumulator configured to accumulate a difference between a target value and a measurement value of the oscillation degree. A value of the wireless signal is determined based on a cumulative signal corresponding to the accumulated difference.
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公开(公告)号:US20180323819A1
公开(公告)日:2018-11-08
申请号:US16032381
申请日:2018-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Ju YUN
IPC: H04B1/403 , H03G3/30 , H03D1/00 , H03F1/56 , H03B5/24 , H03F3/19 , H03F3/24 , H03B5/32 , H03B5/12 , H03B5/08
CPC classification number: H04B1/406 , H03B5/08 , H03B5/1234 , H03B5/1237 , H03B5/24 , H03B5/32 , H03D1/00 , H03F1/565 , H03F3/19 , H03F3/245 , H03F2200/222 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03G3/3042
Abstract: A radio frequency (RF) transceiver includes a first oscillator configured to generate a first oscillation frequency associated with an RF signal, a second oscillator configured to generate a second oscillation frequency associated with a clock frequency, a counter configured to generate a counter output signal using the first oscillation frequency and the second oscillation frequency, and a comparer configured to generate a digital output signal associated with the RF signal by comparing an output value of the counter output signal to a reference value.
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公开(公告)号:US20250166702A1
公开(公告)日:2025-05-22
申请号:US18947724
申请日:2024-11-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyuk LEE , Soon-Wan KWON , Sang Joon KIM , Sungmeen MYUNG , Boyoung SEO , Seok Ju YUN , Kangho LEE
IPC: G11C13/00
Abstract: A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.
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