公开(公告)号：US08759221B2

公开(公告)日：2014-06-24

申请号：US13924817

申请日：2013-06-24

Applicant: Samsung Electronics Co., Ltd

Inventor： Jin-Woo Park ,  Hwan-Sik Lim ,  Eunchul Ahn

IPC: H01L21/302

CPC classification number: H01L21/50 ,  H01L21/563 ,  H01L23/48 ,  H01L23/58 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/00012

Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.

Abstract translation: 封装基板，具有该封装基板的半导体封装以及半导体封装的制造方法。 半导体封装包括半导体芯片，封装基板和模制层。 封装衬底提供安装有半导体芯片的区域。 模制层被配置成模制半导体芯片。 封装基板包括第一开口部分，该第一开口部分提供与半导体芯片电连接的开放区域，并且延伸超过半导体芯片的两侧以与半导体芯片电连接。

公开(公告)号：US09035308B2

公开(公告)日：2015-05-19

申请号：US14197203

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Hyeongmun Kang ,  Taesung Park ,  Eunchul Ahn

IPC: H01L23/58 ,  G01R31/26 ,  H01L23/544 ,  H01L21/3105

CPC classification number: H01L23/544 ,  H01L21/3105 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Abstract translation: 一种半导体封装，包括：半导体衬底; 半导体衬底上的模具层; 以及形成在所述模具层的表面上的标记，所述标记包括基本上不连续地布置在显示区域的垂直和水平方向上的点标记。 标记的单位显示区域内的点标记的有效面积小于单位显示区域的总面积的约一半。