公开(公告)号：US20140008818A1

公开(公告)日：2014-01-09

申请号：US13886758

申请日：2013-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L23/48

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US09035308B2

公开(公告)日：2015-05-19

申请号：US14197203

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Hyeongmun Kang ,  Taesung Park ,  Eunchul Ahn

IPC: H01L23/58 ,  G01R31/26 ,  H01L23/544 ,  H01L21/3105

CPC classification number: H01L23/544 ,  H01L21/3105 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Abstract translation: 一种半导体封装，包括：半导体衬底; 半导体衬底上的模具层; 以及形成在所述模具层的表面上的标记，所述标记包括基本上不连续地布置在显示区域的垂直和水平方向上的点标记。 标记的单位显示区域内的点标记的有效面积小于单位显示区域的总面积的约一半。

公开(公告)号：US20150031170A1

公开(公告)日：2015-01-29

申请号：US14464014

申请日：2014-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L21/768 ,  H01L21/82

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US09087883B2

公开(公告)日：2015-07-21

申请号：US14464014

申请日：2014-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L21/50 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/82 ,  H01L21/56

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US08890333B2

公开(公告)日：2014-11-18

申请号：US13886758

申请日：2013-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L29/40

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。