公开(公告)号：US09721957B2

公开(公告)日：2017-08-01

申请号：US14563695

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US11990503B2

公开(公告)日：2024-05-21

申请号：US17376458

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gabjin Nam ,  Youngbin Lee ,  Cheoljin Cho ,  Jaehyoung Choi

IPC: H10B53/30 ,  G11C11/22 ,  H01L49/02

CPC classification number: H01L28/60 ,  H10B53/30 ,  G11C11/22 ,  H01L28/55

Abstract: Provided is a method of fabricating a capacitor. The method of fabricating a capacitor may include forming a first electrode, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, and applying, between the first electrode and the second electrode, a voltage outside an operating voltage range applied during operation or a current outside an operating current range applied during operation.

公开(公告)号：US09997523B2

公开(公告)日：2018-06-12

申请号：US15631308

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L21/82 ,  H01L27/11 ,  H01L51/00 ,  H01L51/05 ,  H01L27/28

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US20170294441A1

公开(公告)日：2017-10-12

申请号：US15631308

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L27/28 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US20230165012A1

公开(公告)日：2023-05-25

申请号：US18049366

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gabjin Nam ,  Bongjin Kuh ,  Musarrat Hasan ,  Geonju Park ,  Yongho Ha

IPC: H01L27/1159

CPC classification number: H01L27/1159

Abstract: A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.

公开(公告)号：US20150179655A1

公开(公告)日：2015-06-25

申请号：US14563695

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L51/00 ,  H01L51/05 ,  H01L27/28

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Abstract translation: 静态随机存取存储器（SRAM）单元可以包括第一上拉晶体管，第一下拉晶体管，第二上拉晶体管，第二下拉晶体管，第一存取晶体管和第二存取晶体管， 全部在6晶体管SRAM单元中耦合在一起，其中每个晶体管被配置为垂直沟道晶体管。