公开(公告)号：US12149247B2

公开(公告)日：2024-11-19

申请号：US17932023

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yoo-Chang Sung ,  Jeongdon Ihm ,  Hojun Chang ,  Jinseok Heo

IPC: H03K21/02 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40 ,  G11C7/10 ,  G11C7/22

Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

公开(公告)号：US20240119997A1

公开(公告)日：2024-04-11

申请号：US18221598

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： GARAM CHOI ,  Yonghun Kim ,  Jaewoo Lee ,  Kihan Kim ,  Hojun Chang

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076

Abstract: A semiconductor chip includes a write clock buffer, a voltage regulator, a process calibration circuit and a temperature calibration circuit. The voltage regulator generates plural regulated voltages. The process calibration circuit output one of the regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip. The temperature calibration circuit track a temperature variation of the semiconductor chip in real time, performs analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and outputs the analog-calibrated bias voltage to the write clock buffer.

公开(公告)号：US11705172B2

公开(公告)日：2023-07-18

申请号：US17567306

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C29/023

Abstract: A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

公开(公告)号：US20240038798A1

公开(公告)日：2024-02-01

申请号：US18220445

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun Chang ,  Hyochul Kim ,  Junhyuk Moon ,  Youngho Jung

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14636

Abstract: Disclosed is a color filter according to an example embodiment, an image sensor, and an electronic apparatus having the image sensor. The color filter includes a first dielectric layer, a second dielectric layer on the first dielectric layer, and a plurality of metal elements buried in both of the first dielectric layer and the second dielectric layer in lateral contact with each of the first dielectric layer and the second dielectric layer.

公开(公告)号：US11869574B2

公开(公告)日：2024-01-09

申请号：US17674908

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C11/4076 ,  G11C11/4093 ,  H03K3/017 ,  H01L25/18 ,  H01L25/065

CPC classification number: G11C11/4076 ,  G11C11/4093 ,  H03K3/017 ,  H01L25/0657 ,  H01L25/18

Abstract: A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

公开(公告)号：US20230223941A1

公开(公告)日：2023-07-13

申请号：US17932023

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yoo-Chang Sung ,  Jeongdon Ihm ,  Hojun Chang ,  Jinseok Heo

IPC: H03K21/02 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40

CPC classification number: H03K21/026 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40

Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

公开(公告)号：US20230029968A1

公开(公告)日：2023-02-02

申请号：US17674908

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C11/4076 ,  G11C11/4093 ,  H03K3/017

Abstract: A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.