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公开(公告)号：US11791791B2
公开(公告)日：2023-10-17
申请号：US17352487
申请日：2021-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Yoo-Chang Sung , Wangsoo Kim , Indal Song
CPC classification number: H03G5/165 , H03F1/26 , H03F3/45183 , H03F3/68 , H04B1/16 , H03F2200/129 , H03F2200/165 , H03F2200/267 , H03F2200/375 , H03F2203/45212
Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
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公开(公告)号：US12149247B2
公开(公告)日：2024-11-19
申请号：US17932023
申请日：2022-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaewoo Lee , Yoo-Chang Sung , Jeongdon Ihm , Hojun Chang , Jinseok Heo
IPC: H03K21/02 , G11C11/4076 , G11C11/4093 , H03K23/40 , G11C7/10 , G11C7/22
Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.
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公开(公告)号：US20210313945A1
公开(公告)日：2021-10-07
申请号：US17352487
申请日：2021-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Yoo-Chang Sung , Wangsoo Kim , Indal Song
Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
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公开(公告)号：US11075610B2
公开(公告)日：2021-07-27
申请号：US16654558
申请日：2019-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Yoo-Chang Sung , Wangsoo Kim , Indal Song
Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
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公开(公告)号：US20190140628A1
公开(公告)日：2019-05-09
申请号：US16026145
申请日：2018-07-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： WANGSOO KIM , Hangi Jung , Kiduk Park , Yoo-Chang Sung , Jae-Hun Jung , Cheongryong Cho , Hun-dae Choi
IPC: H03K5/13
CPC classification number: H03K5/13 , H03K2005/00019 , H04B1/04
Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
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Patent Agency Ranking
公开(公告)号：US10725682B2
公开(公告)日：2020-07-28
申请号：US16103078
申请日：2018-08-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wang-Soo Kim , Jung-Hwan Choi , Ki-Duk Park , Yoo-Chang Sung , Jin-Sung Youn , Chang-Kyo Lee , Ju-Ho Jeon , Jin-Seok Heo
IPC: G06F12/00 , G06F3/06 , H04L25/03 , G11C29/02 , G11C5/04 , G11C29/12 , G11C11/407 , H01L25/18 , G11C29/44
Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.
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公开(公告)号：US10367490B2
公开(公告)日：2019-07-30
申请号：US16026145
申请日：2018-07-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wangsoo Kim , Hangi Jung , Kiduk Park , Yoo-Chang Sung , Jae-Hun Jung , Cheongryong Cho , Hun-Dae Choi
Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
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公开(公告)号：US20230223941A1
公开(公告)日：2023-07-13
申请号：US17932023
申请日：2022-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaewoo Lee , Yoo-Chang Sung , Jeongdon Ihm , Hojun Chang , Jinseok Heo
IPC: H03K21/02 , G11C11/4076 , G11C11/4093 , H03K23/40
CPC classification number: H03K21/026 , G11C11/4076 , G11C11/4093 , H03K23/40
Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.
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公开(公告)号：US11249662B2
公开(公告)日：2022-02-15
申请号：US16914724
申请日：2020-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wang-Soo Kim , Jung-Hwan Choi , Ki-Duk Park , Yoo-Chang Sung , Jin-Sung Youn , Chang-Kyo Lee , Ju-Ho Jeon , Jin-Seok Heo
IPC: G06F12/00 , G06F3/06 , H04L25/03 , G11C29/02 , G11C5/04 , G11C29/12 , G11C11/407 , H01L25/18 , G11C29/44
Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.
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公开(公告)号：US20200313638A1
公开(公告)日：2020-10-01
申请号：US16654558
申请日：2019-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Yoo-Chang Sung , Wangsoo Kim , Indal Song
Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
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