公开(公告)号：US20210111070A1

公开(公告)日：2021-04-15

申请号：US16785732

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Yong BAE ,  Hoon Seok SEO ,  Ki Hyun PARK ,  Hak-Sun LEE

IPC: H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

公开(公告)号：US20240145345A1

公开(公告)日：2024-05-02

申请号：US18209206

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggil KIM ,  Hoon Seok SEO ,  Yungbae KIM ,  Wookyung YOU

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.

公开(公告)号：US20200098620A1

公开(公告)日：2020-03-26

申请号：US16411439

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20240204107A1

公开(公告)日：2024-06-20

申请号：US18532230

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Koo KANG ,  Woo Kyung YOU ,  Min Jae KANG ,  Koung Min RYU ,  Hoon Seok SEO ,  Woo Jin LEE ,  Jun Chae LEE

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.

公开(公告)号：US20190148289A1

公开(公告)日：2019-05-16

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok SEO ,  Jong Min BAEK ,  Su Hyun BARK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Eui Bok LEE

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US20240087956A1

公开(公告)日：2024-03-14

申请号：US18510732

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20230114920A1

公开(公告)日：2023-04-13

申请号：US18079998

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20210166974A1

公开(公告)日：2021-06-03

申请号：US17174409

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.