公开(公告)号：US20170213586A1

公开(公告)日：2017-07-27

申请号：US15331970

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Hui-Kap YANG

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

公开(公告)号：US20190304565A1

公开(公告)日：2019-10-03

申请号：US16283650

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun KIM ,  Yoon-Na OH ,  Hyung-Jin KIM ,  Hui-Kap YANG ,  Jang-Woo RYU

IPC: G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C8/12

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US20220238178A1

公开(公告)日：2022-07-28

申请号：US17723200

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun KIM ,  Yoon-Na OH ,  Hyung-Jin KIM ,  Hui-Kap YANG ,  Jang-Woo RYU

IPC: G11C29/00 ,  G11C29/24 ,  G11C8/12 ,  G11C29/44

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US20210233604A1

公开(公告)日：2021-07-29

申请号：US17216160

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun KIM ,  Yoon-Na OH ,  Hyung-Jin KIM ,  Hui-Kap YANG ,  Jang-Woo RYU

IPC: G11C29/00 ,  G11C8/12 ,  G11C29/44 ,  G11C29/24

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US20170140810A1

公开(公告)日：2017-05-18

申请号：US15340345

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Jun CHOI ,  Hui-Kap YANG

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40603 ,  G11C11/40607 ,  G11C11/40618

Abstract: A memory device includes a memory bank, a command control logic circuit, a row selection circuit, a refresh controller and a collision controller. The memory bank includes a plurality of memory blocks. The command control logic circuit decodes commands received from a memory controller to generate control signals. The command control logic receives an active command for an access operation during a refresh operation. The row selection circuit performs the access operation and the refresh operation with respect to the memory bank. The refresh controller controls the refresh operation. The collision controller generates a wait signal causing a delay of the access operation based on a result of a comparison of a row address associated with the access operation and a refresh address associated with the refresh operation.