公开(公告)号：US09953981B2

公开(公告)日：2018-04-24

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L21/4763 ,  H01L27/108 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

公开(公告)号：US09754944B2

公开(公告)日：2017-09-05

申请号：US14539558

申请日：2014-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

公开(公告)号：US11062818B2

公开(公告)日：2021-07-13

申请号：US14588734

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-jun Jeong ,  Seong-jun Park ,  Hyeon-jin Shin ,  Yea-hyun Gu ,  Hyoung-sub Kim ,  Jae-hyun Yang

IPC: B32B9/00 ,  H01B1/04 ,  C23C16/02 ,  C23C16/455 ,  H01L29/51 ,  H01L29/778 ,  C23C16/40 ,  H01L29/16

Abstract: Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.

公开(公告)号：US09613966B2

公开(公告)日：2017-04-04

申请号：US14697782

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Sung-eui Kim

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

公开(公告)号：US10037999B2

公开(公告)日：2018-07-31

申请号：US14591732

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Sung-eui Kim ,  Hoon Jeong

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.

公开(公告)号：US20160322362A1

公开(公告)日：2016-11-03

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

Abstract translation: 一种制造半导体器件的方法包括：通过在第一方向上设置的第一凹槽彼此间隔开的位线结构，在第一方向上延伸并且在垂直于第一方向的第二方向上彼此间隔开，在基底上， 线被埋葬 在位线结构的两个侧壁上形成多层隔板; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。