公开(公告)号：US09953981B2

公开(公告)日：2018-04-24

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L21/4763 ,  H01L27/108 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

公开(公告)号：US10896966B2

公开(公告)日：2021-01-19

申请号：US16385245

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-jin Lee ,  Bong-soo Kim ,  Ji-young Kim ,  Ho-rim Yoo

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including a first region and a second region, a buried gate structure located on a first recess in the first region of the substrate, and a recess gate structure located on a second recess in the second region of the substrate, wherein the buried gate structure is buried in the substrate, an upper portion of the recess gate structure is not buried in the substrate, and a first work function adjustment layer in the buried gate structure may include a material identical to a material included in a second work function layer of the recess gate structure.

公开(公告)号：US09548260B2

公开(公告)日：2017-01-17

申请号：US14175305

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Park ,  Dae-ik Kim ,  Ji-young Kim ,  Nak-jin Son ,  Yoo-sang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/485 ,  H01L27/108 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。

公开(公告)号：US10317798B2

公开(公告)日：2019-06-11

申请号：US15407628

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-oh Park ,  Sang-chul Shin ,  Chang-hwan Kim ,  Ji-young Kim

IPC: G03F7/20 ,  G03F7/095 ,  G11C7/06 ,  G11C8/08 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  G03F7/00

Abstract: A method of forming a pattern of a semiconductor device includes: forming a first mask pattern comprising first mask lines extending in a first direction in a cell region and second mask lines extending in the first direction in a first core region, the first mask pattern covering a second core region; forming, on the first mask pattern, a second mask pattern comprising third mask lines extending in a second direction in the cell region and fourth mask lines extending in the second direction in the second core region, the second mask pattern covering the first core region; and forming a third mask pattern by using the second mask pattern, the third mask pattern comprising island-type masks in the cell region, fifth mask lines extending in the first direction in the first core region, and sixth mask lines extending in the second direction in the second core region.

公开(公告)号：US20160322362A1

公开(公告)日：2016-11-03

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

Abstract translation: 一种制造半导体器件的方法包括：通过在第一方向上设置的第一凹槽彼此间隔开的位线结构，在第一方向上延伸并且在垂直于第一方向的第二方向上彼此间隔开，在基底上， 线被埋葬 在位线结构的两个侧壁上形成多层隔板; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。