公开(公告)号：US20160118342A1

公开(公告)日：2016-04-28

申请号：US14986872

申请日：2016-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA

IPC: H01L23/525 ,  H01L27/112 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/62 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract translation: 提供熔丝结构及其吹塑方法。 熔丝结构包括在基板上的导电线，导电线上彼此间隔开的第一和第二通孔，电连接到第一通孔的阴极电极线，电连接到第一通孔的阳极电极线 第二通孔和与阴极和阳极电极线中的至少一个相邻并且与导电线电绝缘的虚设图案。

公开(公告)号：US20160093398A1

公开(公告)日：2016-03-31

申请号：US14753620

申请日：2015-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Ji-Hoon YOON

IPC: G11C17/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/53

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Abstract translation: 存储器件可以包括非易失性存储器单元。 非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。 非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值 大于第四电阻值且大于第四电阻值。

公开(公告)号：US20170200727A1

公开(公告)日：2017-07-13

申请号：US15399243

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon YOON ,  Hyun-Min CHOI

IPC: H01L27/112 ,  H01L23/525

Abstract: A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on a substrate, a first gate insulation pattern between the first active region and the writing gate electrode, a second gate insulation pattern between the second active region and the reading gate electrode, first and second source/drain junction regions in the first and second active regions at sides of the writing and reading gate electrodes, and a connection structure that connects the first and second source/drain junction regions. The first active region has the same conductivity type as the source/drain junction regions. The second active region has a different conductivity type from the source/drain junction regions.

公开(公告)号：US20160163643A1

公开(公告)日：2016-06-09

申请号：US14955554

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Chul-Yong Park

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/7682 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuse devices, and a method of manufacturing the same, include a first metal pattern extending in a first direction to connect a first electrode and a second electrode to each other, a first barrier metal contacting lateral surfaces and a bottom surface of the first metal pattern, and a first capping insulation layer contacting a top surface of the first metal pattern, wherein the first metal pattern includes an exposed region, the first barrier metal or the first capping insulation layer not contacting a top surface or a bottom surface of the exposed region.

Abstract translation: 电熔丝装置及其制造方法包括：第一金属图案，其沿第一方向延伸以将第一电极和第二电极彼此连接;第一阻挡金属接触侧表面和第一 金属图案和与第一金属图案的顶表面接触的第一封盖绝缘层，其中第一金属图案包括暴露区域，第一阻挡金属或第一封盖绝缘层不接触第一金属图案的顶表面或底表面 暴露区域。

公开(公告)号：US20160005494A1

公开(公告)日：2016-01-07

申请号：US14713458

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  In-Gyu PARK ,  Jung-Hak SONG

IPC: G11C29/50 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/027 ,  G11C2029/1206 ,  G11C2029/5006

Abstract: An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.

Abstract translation: 提供电子熔断器测试装置。 电熔丝测试装置可以包括第一晶体管和连接到第一晶体管的源极/漏极端子的熔丝阵列。 熔丝阵列可以包括n个熔丝组，每个熔丝组可以包括在一端和另一端之间彼此串联连接的一端，另一端和m个第一熔丝元件， 熔丝组可以彼此连接，并且每个熔丝组的另一端可以连接到第一晶体管的源极/漏极端子，并且n和m是等于或大于2的自然数。

公开(公告)号：US20170047335A1

公开(公告)日：2017-02-16

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Jihoon YOON ,  SUNGMAN LIM

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。

公开(公告)号：US20170047287A1

公开(公告)日：2017-02-16

申请号：US15228498

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53257

Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

Abstract translation: 半导体器件的eFuse结构可以包括在衬底上形成在第一电平的第一金属，在第一电平和衬底之间的第二电平处形成的第二金属，形成在第二电平和第二电平之间的第三电平的第三金属， 所述基板，将所述第一金属连接到所述第二金属的第一通孔，以及将所述第二金属连接到所述第三金属的第二通孔。 第一金属可以包括沿第一方向延伸的第一部分，在第一方向上延伸并且与第一部分相邻的第二部分，以及将第一部分连接到第二部分的第三部分。 第一部分和第二部分之间的第一距离可以大于垂直于第一方向的第二方向上的第二部分的宽度。

公开(公告)号：US20150108602A1

公开(公告)日：2015-04-23

申请号：US14304750

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Ji-Hoon YOON ,  Sung-Man LIM

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。

公开(公告)号：US20170256493A1

公开(公告)日：2017-09-07

申请号：US15598627

申请日：2017-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI

IPC: H01L23/525 ,  H01L23/522 ,  H01L27/112 ,  H01L23/528

CPC classification number: H01L23/5256 ,  G11C29/785 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.

公开(公告)号：US20170155756A1

公开(公告)日：2017-06-01

申请号：US15362150

申请日：2016-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang-Youl KIM ,  Jun-Tai KIM ,  Min-Ho BAE ,  Beak-Kwon SON ,  Jung-Yeol AN ,  Chui-Min CHOI ,  Yang-Su KIM ,  Jae-Mo YANG ,  Nam-Woog LEE ,  Keun-Won JANG ,  Hyun-Min CHOI

IPC: H04M3/00 ,  G10L21/0232

CPC classification number: H04M3/002 ,  G10L21/0208 ,  G10L2021/02165 ,  H04B3/23 ,  H04M9/085

Abstract: A method, device, a non-transitory computer-readable recording medium for controlling a voice signal by an electronic device including a first microphone, a second microphone, a communication interface, and a processor are provided. The method includes acquiring a first voice signal by using the first microphone; acquiring a second voice signal by using the second microphone; confirming a telephone call mode for performing, by the electronic device, a telephone call with an external electronic device; adjusting a first output attribute corresponding to the first voice signal or a second output attribute corresponding to the second voice signal, based on the telephone call mode; and transmitting the adjusted first voice signal or the adjusted second voice signal to the external electronic device by using the communication interface.