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1.
公开(公告)号:US20240332185A1
公开(公告)日:2024-10-03
申请号:US18454832
申请日:2023-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: TAE SUN KIM , WONHYUK HONG , JONGJIN LEE , KANG-ILL SEO
IPC: H01L23/528 , H01L21/768 , H01L29/417
CPC classification number: H01L23/5286 , H01L21/76895 , H01L29/41766
Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a backside power distribution network structure (BSPDNS), a logic device region and a passive device region on the BSPDNS, a backside insulating layer including a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region, the passive device region including a semiconductor layer that is in the backside insulating layer, and a dam separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.
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公开(公告)号:US20230326848A1
公开(公告)日:2023-10-12
申请号:US18086340
申请日:2022-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JONGJIN LEE , EUN-JI JUNG , Hobin JUNG , HYUN CHO
IPC: H01L23/522 , H01L27/092 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/423 , H01L29/775 , H01L21/768 , H01L21/8238 , H01L29/66
CPC classification number: H01L23/5226 , H01L27/092 , H01L23/5283 , H01L23/53238 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L21/823807 , H01L21/823871 , H01L29/775
Abstract: Provided is a semiconductor device including a substrate including an active region, transistors on the substrate, a first interlayer insulating layer and a second interlayer insulating layer on the transistors, a first interconnection line in an upper portion of the first interlayer insulating layer, and a second interconnection line in the second interlayer insulating layer, wherein the first interconnection line includes a first barrier pattern, a first liner, and a first conductive pattern, wherein the second interconnection line includes a second barrier pattern, a second liner, and a second conductive pattern, wherein first height between an uppermost portion of a top surface of the first conductive pattern and a lowermost portion of a top surface of the first liner is greater than a second height between an uppermost portion of a top surface of the second conductive pattern and a lowermost portion of a top surface of the second liner.
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公开(公告)号:US20230064127A1
公开(公告)日:2023-03-02
申请号:US18053487
申请日:2022-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: JONGJIN LEE , Kyungwook Kim , Rakhwan Kim , Seungyong Yoo , Eun-Ji Jung
IPC: H01L23/522 , H01L23/532 , H01L29/45
Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.
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公开(公告)号:US20220068805A1
公开(公告)日:2022-03-03
申请号:US17235984
申请日:2021-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: JONGJIN LEE , KYUNGWOOK KIM , RAKHWAN KIM , SEUNGYONG YOO , EUN-JI JUNG
IPC: H01L23/522 , H01L23/532 , H01L29/45
Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.
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5.
公开(公告)号:US20160097981A1
公开(公告)日:2016-04-07
申请号:US14867292
申请日:2015-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: SANGJOON HONG , JONGJIN LEE , HiKUK LEE , SANGDON JANG , Inbae CHANG
CPC classification number: G03F7/16 , G03F7/70383 , G03F7/70791 , G03F7/7085
Abstract: An optical apparatus and a manufacturing method using the optical apparatus are disclosed. The optical apparatus includes a stage supporting a substrate, first optical systems providing a first light onto the substrate, a gantry supporting the first optical systems to transfer them on the stage, and second optical systems disposed between the gantry and the stage and detecting displacement of the first optical systems. Each of the second optical systems includes a beam source generating a second light different with the first light, and sensor arrays for sensing the second light provided to the first optical systems to detect displacement of the first optical systems.
Abstract translation: 公开了一种使用该光学装置的光学装置和制造方法。 光学装置包括支撑基板的台,在基板上提供第一光的第一光学系统,支撑第一光学系统以将它们传送到台上的台架,以及设置在台架与台之间的第二光学系统, 第一个光学系统。 每个第二光学系统包括产生与第一光不同的第二光的光束源和用于感测提供给第一光学系统的第二光以检测第一光学系统的位移的传感器阵列。
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