公开(公告)号：US10211196B2

公开(公告)日：2019-02-19

申请号：US15234532

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyok Ko ,  Min-Chang Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78 ,  H01L29/66

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

公开(公告)号：US09799641B2

公开(公告)日：2017-10-24

申请号：US14809299

申请日：2015-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/027

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

公开(公告)号：US10134723B2

公开(公告)日：2018-11-20

申请号：US15708452

申请日：2017-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

公开(公告)号：US20180012883A1

公开(公告)日：2018-01-11

申请号：US15708452

申请日：2017-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/027

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

公开(公告)号：US09093287B2

公开(公告)日：2015-07-28

申请号：US14082742

申请日：2013-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Min-Chang Ko ,  Chang-Su Kim ,  Kyoung-Ki Jeon

IPC: H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/07 ,  H01L27/02 ,  H01L29/861

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L27/0255 ,  H01L27/0705 ,  H01L29/8611 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract translation: 提供一种制造二极管的方法。 N型阱区形成在N型外延层的第一上部。 P型漂移区形成在N型外延层的第二上部。 在N型阱区中形成N型掺杂区。 在P型漂移区域中形成P型掺杂区域。 在P型漂移区域中形成隔离结构。 隔离结构设置在P型掺杂区域和N型阱区域之间。 第一电极形成在N型外延层的一部分上。 N型外延层的部分配置在N型阱区域和P型漂移区域之间。 第一电极与隔离结构的一部分重叠。 形成连接结构以电耦合N型掺杂区域和第一电极。