公开(公告)号：US20140332883A1

公开(公告)日：2014-11-13

申请号：US14089274

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Kwon ,  Hee-Soo Kang ,  Han-Gu Kim ,  Woo-Jin Seo ,  Ki-Tae Lee ,  Jae-Gon Lee ,  Chan-Hee Jeon

IPC: H01L27/088

CPC classification number: H01L27/0886 ,  H01L27/0266 ,  H01L27/1211

Abstract: A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged. A dummy gate electrode is formed between the first and second gate electrodes. A first drain region is formed between the first gate electrode and the dummy gate electrode. A second drain region is formed between the dummy gate electrode and the second gate electrode. A source region facing the second drain region is formed. A first drain plug relatively close to the dummy gate electrode, relatively far from the second gate electrode, and connected to the second drain region is formed. The second gate electrode is arranged between the second drain region and the source region. Each of the first and second gate electrodes covers a side surface of the fin-shaped active region.

Abstract translation: 鳍状有源区限定在基底上。 布置了与鳍状有源区交叉的第一和第二栅电极。 在第一和第二栅电极之间形成虚拟栅电极。 在第一栅电极和伪栅电极之间形成第一漏区。 在虚拟栅极电极和第二栅极电极之间形成第二漏极区域。 形成面向第二漏极区域的源极区域。 形成相对靠近第二栅电极并与第二漏极区连接的虚拟栅电极的第一漏极插头。 第二栅极布置在第二漏极区域和源极区域之间。 第一和第二栅电极中的每一个覆盖鳍状有源区的侧表面。

公开(公告)号：US11108229B2

公开(公告)日：2021-08-31

申请号：US16038744

申请日：2018-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Pil Jang ,  Chang-Su Kim ,  Han-Gu Kim ,  Moon-Seok Yang ,  Kyoung-Ki Jeon

IPC: H02H9/04 ,  H01L27/02 ,  H01L29/872 ,  H01L29/06

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a transient-state detection circuit configured to generate a dynamic triggering signal based on a voltage change rate of a voltage on a first power rail; a voltage detection circuit configured to generate a static triggering signal based on the voltage on the first power rail; a trigger circuit configured to generate a discharge control signal based on the dynamic triggering signal and the static triggering signal; and a main discharge circuit configured to discharge an electric charge from the first power rail to a second power rail based on the discharge control signal.

公开(公告)号：US10211196B2

公开(公告)日：2019-02-19

申请号：US15234532

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyok Ko ,  Min-Chang Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78 ,  H01L29/66

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

公开(公告)号：US10318678B2

公开(公告)日：2019-06-11

申请号：US14254337

申请日：2014-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wook Lee ,  Han-Gu Kim ,  Young-Keun Lee ,  Jong-Sung Jeon

IPC: G06F17/50

Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.

公开(公告)号：US10134723B2

公开(公告)日：2018-11-20

申请号：US15708452

申请日：2017-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

公开(公告)号：US20180012883A1

公开(公告)日：2018-01-11

申请号：US15708452

申请日：2017-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/027

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

公开(公告)号：US09093287B2

公开(公告)日：2015-07-28

申请号：US14082742

申请日：2013-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Min-Chang Ko ,  Chang-Su Kim ,  Kyoung-Ki Jeon

IPC: H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/07 ,  H01L27/02 ,  H01L29/861

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L27/0255 ,  H01L27/0705 ,  H01L29/8611 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract translation: 提供一种制造二极管的方法。 N型阱区形成在N型外延层的第一上部。 P型漂移区形成在N型外延层的第二上部。 在N型阱区中形成N型掺杂区。 在P型漂移区域中形成P型掺杂区域。 在P型漂移区域中形成隔离结构。 隔离结构设置在P型掺杂区域和N型阱区域之间。 第一电极形成在N型外延层的一部分上。 N型外延层的部分配置在N型阱区域和P型漂移区域之间。 第一电极与隔离结构的一部分重叠。 形成连接结构以电耦合N型掺杂区域和第一电极。

公开(公告)号：US10121776B2

公开(公告)日：2018-11-06

申请号：US15364890

申请日：2016-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Jun Song ,  Young-Min Kim ,  Chang-Su Kim ,  Han-Gu Kim

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/866 ,  H01L23/535 ,  H01L29/786 ,  H01L27/12

Abstract: A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.

公开(公告)号：US10020231B2

公开(公告)日：2018-07-10

申请号：US15443498

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hee Jeon ,  Eun-Kyoung Kwon ,  Il-Ryong Kim ,  Han-Gu Kim ,  Woo-Jin Seo ,  Ki-Tae Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/266 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0288 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

公开(公告)号：US09799641B2

公开(公告)日：2017-10-24

申请号：US14809299

申请日：2015-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyok Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/027

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.